公开(公告)号：US06649473B1

公开(公告)日：2003-11-18

申请号：US10330777

申请日：2002-12-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L21/28273

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract translation: 一种制造闪存的浮动栅极的方法。 在半导体衬底上形成有源区。 在有源区域中依次形成第一绝缘层，第一导电层和掩模层。 去除掩模层的一部分以形成第一开口。 形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。 在第二导电层上形成第二绝缘层以填充第一开口。 进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。 去除第二和第三绝缘层以形成第二开口。 第四绝缘层填充在第二开口中。 除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。

公开(公告)号：US06486032B1

公开(公告)日：2002-11-26

申请号：US10174672

申请日：2002-06-18

Applicant: Chih-Hui Lin ,  Chung-Lin Huang

Inventor： Chih-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method for fabricating the control gate and floating gate of a flash memory cell. An active area is firstly formed on a semiconductor substrate, followed by the formation of a first insulating layer, a first conductive layer and a first masking layer. A first opening is then formed by partially removing the first masking layer, and a floating gate oxide layer is formed by oxidation. The remaining first masking layer is removed, followed by forming a sacrificial layer, which is then partially removed to define a second opening. The remaining sacrificial layer is used as a hard mask to partially remove the first conductive layer and the first insulating layer to form a third opening. A second insulating layer is formed to fill the third opening to form an insulating plug. Part of the first conductive layer and the first insulating layer are removed to form a floating gate, followed by forming a third insulating layer and a second conductive layer. The insulating plug is then used as stop layer to remove part of the second conductive layer and third insulating layer to form a control gate.

Abstract translation: 一种用于制造闪存单元的控制栅极和浮置栅极的方法。 首先在半导体衬底上形成有源区，然后形成第一绝缘层，第一导电层和第一掩模层。 然后通过部分去除第一掩模层形成第一开口，并且通过氧化形成浮栅氧化层。 除去剩余的第一掩蔽层，随后形成牺牲层，然后部分地去除牺牲层以限定第二开口。 剩余的牺牲层用作硬掩模以部分地去除第一导电层和第一绝缘层以形成第三开口。 形成第二绝缘层以填充第三开口以形成绝缘插头。 去除第一导电层和第一绝缘层的一部分以形成浮置栅极，随后形成第三绝缘层和第二导电层。 然后将绝缘插头用作停止层以去除部分第二导电层和第三绝缘层以形成控制栅极。

公开(公告)号：US06475894B1

公开(公告)日：2002-11-05

申请号：US10052622

申请日：2002-01-18

Applicant: Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

Inventor： Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

IPC: H01L218247

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.

Abstract translation: 本发明提供一种制造闪速存储器的浮动栅极的方法。 首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。 然后形成栅极氧化物层和第一多晶硅层。 第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。 牺牲绝缘体填充到凹部中。 然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。 在第一多晶硅层的侧壁上形成多晶硅间隔物。 在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。 然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。 最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。 在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。 因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。

公开(公告)号：US08873280B2

公开(公告)日：2014-10-28

申请号：US13282771

申请日：2011-10-27

Applicant: Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: G11C11/00

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/08

Abstract: A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.

Abstract translation: 自旋传递转矩随机存取存储器包括物质单元，源极线单元，绝缘单元，晶体管单元，MTJ单元和位线单元。 物质单元包括物质层。 源极线单元包括形成在物质层内部的多个源极线。 晶体管单元包括分别设置在源极线上的多个晶体管。 每个晶体管包括形成在每个对应源极线上的源极区域，形成在源极区域上方的漏极区域，形成在源极区域和漏极区域之间的沟道区域，以及围绕源极区域，漏极区域和 通道区域。 MTJ单元包括分别设置在晶体管上的多个MTJ结构。 位线单元包括设置在MTJ单元上的至少一个位线。

公开(公告)号：US08703575B2

公开(公告)日：2014-04-22

申请号：US13421996

申请日：2012-03-16

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/76 ,  H01L21/00

CPC classification number: H01L21/76224

Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

Abstract translation: 本公开涉及形成隔离区域的方法。 该方法包括以下步骤：提供具有第一类型的离子掺杂剂的衬底，其中衬底具有形成在单元区域上的多个沟槽和衬底的单元区域之间的隔离区域与沟槽的侧壁 其上形成有氧化层，并且沟槽填充有金属结构; 从隔离区的沟槽移除金属结构; 在隔离区的沟槽下方将第二类型的离子注入到衬底中; 并用绝缘结构填充所有沟槽，其中隔离区域的沟槽由绝缘结构完全填充以形成非金属隔离区域。

公开(公告)号：US20130252397A1

公开(公告)日：2013-09-26

申请号：US13476251

申请日：2012-05-21

Applicant: SHIN-BIN HUANG ,  CHENG-YEH HSU ,  CHUNG-LIN HUANG

Inventor： SHIN-BIN HUANG ,  CHENG-YEH HSU ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

Abstract translation: 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US08486801B2

公开(公告)日：2013-07-16

申请号：US13297276

申请日：2011-11-16

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66545

Abstract: A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

Abstract translation: DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。 掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。 此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。 然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。 埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。

公开(公告)号：US08471320B2

公开(公告)日：2013-06-25

申请号：US13343668

申请日：2012-01-04

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L28/90

Abstract: A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.

Abstract translation: 存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

公开(公告)号：US20130062676A1

公开(公告)日：2013-03-14

申请号：US13239364

申请日：2011-09-21

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L29/40114

Abstract: A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

Abstract translation: 闪速存储器结构包括半导体衬底，半导体衬底上的栅极电介质层，栅极介电层上的浮置栅极，保形地覆盖浮置栅极的电容器电介质层，其中电容器介电层形成顶表面和四个侧壁表面 ; 以及覆盖顶表面和四个侧壁表面的隔离的导电盖层。

公开(公告)号：US08373220B1

公开(公告)日：2013-02-12

申请号：US13224561

申请日：2011-09-02

Applicant: Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

Abstract translation: 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元形成在第一电介质层上。 每个数据存储单元包括形成在第一介电层上的两个浮置栅极，分别形成在两个浮置栅极上的两个栅极间电介质层，分别形成在两个栅极间电介质层上的两个控制栅极， 第一电介质层，两个浮置栅极之间，两个栅极间电介质层之间以及两个控制栅极之间，以及形成在第一介电层上并围绕并连接两个浮动栅极的第三介质层， - 门电介质层和两个控制门。