公开(公告)号：US20130083593A1

公开(公告)日：2013-04-04

申请号：US13625923

申请日：2012-09-25

Applicant: Crocus Technology SA

Inventor： Ioan Lucian Prejbeanu ,  Lucien Lombard

IPC: H01L29/82 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C11/00 ,  G11C11/1673 ,  G11C11/1675

Abstract: MRAM cell comprising a magnetic tunnel junction comprising a storage layer having a net storage magnetization being adjustable when the magnetic tunnel junction is at a high temperature threshold and being pinned at a low temperature threshold; a sense layer having a reversible sense magnetization; and a tunnel barrier layer between the sense and storage layers; at least one of the storage and sense layer comprising a ferrimagnetic 3d-4f amorphous alloy material comprising a sub-lattice of 3d transition metals atoms providing a first magnetization and a sub-lattice of 4f rare-earth atoms providing a second magnetization, such that at a compensation temperature of said at least one of the storage layer and the sense layer, the first magnetization and the second magnetization are substantially equal. The disclosed MRAM cell can be written and read using a small writing and reading field, respectively.

Abstract translation: MRAM单元包括磁隧道结，其包括存储层，所述存储层具有当磁性隧道结处于高温阈值并被固定在低温阈值时可净化的净存储磁化; 具有可逆感测磁化的感测层; 以及感测层和存储层之间的隧道势垒层; 所述存储和感测层中的至少一个包括铁氧体3d-4f非晶合金材料，其包含提供第一磁化的3d过渡金属原子的子晶格和提供第二磁化的4f稀土原子的子晶格，使得 在所述存储层和感测层中的至少一个的补偿温度下，第一磁化强度和第二磁化强度基本相等。 可以分别使用小的写入和读取字段来写入和读取所公开的MRAM单元。

公开(公告)号：US20240027551A1

公开(公告)日：2024-01-25

申请号：US18256494

申请日：2021-12-09

Applicant: CROCUS Technology SA

Inventor： Jeffrey Childress ,  Nikita Strelkov

IPC: G01R33/09

CPC classification number: G01R33/098

Abstract: Magnetoresistive element including a reference layer having a fixed reference magnetization, a sense layer having a free sense magnetization and a tunnel barrier layer between the reference layer and the sense layer; the magnetoresistive element being configured to measure an external magnetic field oriented substantially perpendicular to the plane of the layers. The reference magnetization being oriented substantially perpendicular to the plane of the reference layer. The sense magnetization including a vortex configuration in the absence of an external magnetic field, the vortex configuration being substantially parallel to the plane of the sense layer and having a vortex core magnetization along an out-of-plane axis substantially perpendicular to the plane of the sense layer.

公开(公告)号：US20230296703A1

公开(公告)日：2023-09-21

申请号：US18245380

申请日：2021-09-14

Applicant: CROCUS Technology SA

Inventor： Andrey Timopheev ,  Nikita Strelkov ,  Jeffrey Childress

IPC: G01R33/09

CPC classification number: G01R33/098

Abstract: A magnetoresistive element for a 2D magnetic sensor, the magnetoresistive element including a tunnel barrier layer included between a reference layer having a reference magnetization and a sense layer having a sense magnetization. The sense layer includes a sense synthetic antiferromagnetic structure including a first sense sublayer in contact with the tunnel barrier layer and separated from a second sense sublayer by a first non-magnetic spacer layer such that the first sense sublayer is antiferromagnetically coupled to the second sense sublayer. The sense layer is configured such that a sense magnetic ratio ΔM defined as:




Δ
M
=


M

s

F
M
2



t

F
M
2


−
M

s

F
M
1



t

F
M
1




M

s

F
M
2



t

F
M
2


+
M

s

F
M
1



t

F
M
1








wherein MSFM1 and MSFM2 are the spontaneous magnetizations of the first and second sense sublayers and tFM1 and tFM2 are the thicknesses of the first and second sense sublayers; and wherein the sense magnetic ratio is between 0.1 and 0.25.

公开(公告)号：US20230119854A1

公开(公告)日：2023-04-20

申请号：US17905214

申请日：2021-02-22

Applicant: CROCUS Technology SA

Inventor： Anuraag Mohan ,  Robert Zucker

IPC: G01R33/09 ,  G01R33/00

Abstract: Disclosed is a MTJ sensing circuit for measuring an external magnetic field and including a plurality of MTJ sensor elements connected in a bridge configuration, the MTJ sensing circuit having an input for inputting a bias voltage and generating an output voltage proportional to the external magnetic field multiplied by the bias voltage and a gain sensitivity of the MTJ sensing circuit, wherein the gain sensitivity and the output voltage vary with temperature; the MTJ sensing circuit further including a temperature compensation circuit configured to provide a modulated bias voltage that varies as a function of temperature over a temperature range, such that the output voltage is substantially constant as a function of temperature. Also disclosed is a method for compensating the output voltage for temperature.

公开(公告)号：US11017828B2

公开(公告)日：2021-05-25

申请号：US16633775

申请日：2018-06-25

Applicant: Crocus Technology SA

Inventor： Jeremy Alvarez-Herault ,  Lucien Lombard ,  Quentin Stainer ,  Jeffrey Childress

IPC: G11C11/16 ,  H01F7/02 ,  H03K19/18

Abstract: An apparatus for generating a magnetic field including permanent magnets arranged in a plane, each magnet being spatially separated along the plane from the adjacent magnet by a predetermined spacing, each magnet having a magnetic polarity opposed to the polarity of the adjacent magnet such that a magnetic field of adjacent magnets is oriented substantially perpendicular to the plane and in opposite directions, each magnet being spatially separated in the plane from the adjacent magnet by a nonmagnetic material. A method for programming a magnetic device or sensor device using the apparatus is also described.

公开(公告)号：US10330749B2

公开(公告)日：2019-06-25

申请号：US15543619

申请日：2015-12-23

Applicant: CROCUS Technology SA

Inventor： Sebastien Bandiera

IPC: G01R33/09 ,  G01D5/16 ,  G01R33/00 ,  G11C11/16

Abstract: A magnetic logic unit (MLU) cell for sensing magnetic fields, including: a magnetic tunnel junction including a storage layer having a storage magnetization, a sense layer having a sense magnetization; a tunnel barrier layer between the storage layer and the sense layer; and a pinning layer pinning the storage magnetization at a low threshold temperature and freeing it at a high threshold temperature. The sense magnetization is freely alignable at the low and high threshold temperatures and the storage layer induces an exchange bias field magnetically coupling the sense layer such that the sense magnetization tends to be aligned antiparallel or parallel to the storage magnetization. The tunnel barrier layer is configured for generating an indirect exchange coupling between the tunnel barrier layer and the sense layer providing an additional exchange bias field.

公开(公告)号：US10326421B2

公开(公告)日：2019-06-18

申请号：US16084637

申请日：2017-03-15

Applicant: Crocus Technology SA

Inventor： Yann Conraux ,  Quentin Stainer

IPC: H03F15/00 ,  H01L43/08 ,  H03G7/00 ,  H04R3/00

Abstract: A magnetoresistive-based signal shaping circuit for audio applications includes: a field emitting device configured for receiving an input current signal from an audio signal source and for generating a magnetic field in accordance with the input current signal, and a first magnetoresistive element having a first electrical resistance and electrically connected in series to a second magnetoresistive element having a second electrical resistance. The magnetoresistive-based signal shaping device provides an output signal across the second magnetoresistive element when an input voltage is applied across the first and second magnetoresistive element in series. The output signal is a function of the electrical resistance and yields a dynamic range compression effect. The first and second electrical resistance vary with the magnetic field in an opposite fashion.

公开(公告)号：US10236438B2

公开(公告)日：2019-03-19

申请号：US15652482

申请日：2017-07-18

Applicant: International Business Machines Corporation ,  Crocus Technology SA

Inventor： Anthony J. Annunziata ,  Lucian Prejbeanu ,  Philip L. Trouilloud ,  Daniel C. Worledge

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  G11C11/56

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

公开(公告)号：US10119988B2

公开(公告)日：2018-11-06

申请号：US15324291

申请日：2015-06-30

Applicant: Crocus Technology SA

Inventor： Ali Alaoui

IPC: G01P15/105 ,  G01P15/08 ,  G01P15/18 ,  G01R33/09 ,  G01D5/14

Abstract: An MLU-based accelerometer including: at least one MLU including a tunnel barrier layer between a first magnetic layer having a fixed first magnetization direction and a second magnetic layer having a second magnetization direction that can be varied. A proof-mass includes a ferromagnetic material having a proof-mass magnetization inducing a proof-mass field, the proof-mass being elastically suspended such as to be deflected in at least one direction when subjected to an acceleration vector. The proof-mass is magnetically coupled to the MLU cell via the proof-mass field. A read module is configured for determining a magnetoresistance of each MLU cell such as to determine an acceleration vector from the deflection of the proof-mass relative to any one of the at least one MLU cell.

公开(公告)号：US10115447B2

公开(公告)日：2018-10-30

申请号：US15565505

申请日：2016-04-06

Applicant: CROCUS Technology SA

Inventor： Ali Alaoui

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  H03K19/20 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

Abstract: A logic gate module for performing logic functions including a MRAM cell including a magnetic tunnel junction comprising a sense layer, a storage layer, and a spacer layer. The MRAM cell has a junction resistance determined by the degree of alignment between a sense magnetization of the sense layer and the storage magnetization of the storage layer. The storage magnetization and the sense magnetization are switchable between m directions to store data corresponding to one of m logic states, with m>2, such that the MRAM cell is usable as a n-bit cell with n≥2. The logic gate module further includes a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, such that logic functions can be performed.