公开(公告)号：US10651046B2

公开(公告)日：2020-05-12

申请号：US16154237

申请日：2018-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Brendan O'Brien ,  Martin O'Toole ,  Keith Donegan

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033

Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.

公开(公告)号：US20200135545A1

公开(公告)日：2020-04-30

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. SRIVASTAVA ,  Sipeng GU ,  Sunil K. SINGH ,  Xinyuan DOU ,  Akshey SEHGAL ,  Zhiguo SUN

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US20200119002A1

公开(公告)日：2020-04-16

申请号：US16162373

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： RUILONG XIE ,  WILLIAM TAYLOR ,  HUI ZANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.

公开(公告)号：US20200118927A1

公开(公告)日：2020-04-16

申请号：US16161590

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

IPC: H01L23/525 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

公开(公告)号：US10607893B2

公开(公告)日：2020-03-31

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.

公开(公告)号：US20200098913A1

公开(公告)日：2020-03-26

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Andre LABONTE ,  Daniel CHANEMOUGAME

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US10600876B2

公开(公告)日：2020-03-24

申请号：US15974037

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Rongtao Lu

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.

公开(公告)号：US10593674B1

公开(公告)日：2020-03-17

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L29/78 ,  H01L27/092 ,  H03K19/0948 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US10593555B2

公开(公告)日：2020-03-17

申请号：US15925928

申请日：2018-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun Gao ,  Naved Siddiqui ,  Ankur Arya ,  John R Sporre

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033 ,  H01L21/762 ,  H01L21/3105

Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

公开(公告)号：US20200083102A1

公开(公告)日：2020-03-12

申请号：US16685648

申请日：2019-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.