Method for radar detection and digitally modulated radar robust to IQ imbalance

    公开(公告)号:US12025729B2

    公开(公告)日:2024-07-02

    申请号:US17527796

    申请日:2021-11-16

    Applicant: Imec vzw

    CPC classification number: G01S7/354 G01S7/358 G01S13/325 G01S13/58

    Abstract: A method is provided for facilitating radar detection robust to IQ imbalance. The method comprises the step of generating a radar signal in digital domain comprising a number of M periodic repetitions of a code sequence with a length Lc, multiplied with a progressive phase rotation





    e

    j
    ·

    π
    K

    ·
    n


    ,




    where Lc and M are integers, K is an integer or a non-integer, and n is a discrete integer variable. The method further comprises the step of generating a process input signal in digital domain from a reflection signal corresponding to the radar signal by multiplying the reflection signal with a progressive phase rotation






    e


    -
    j

    ·

    π
    K

    ·
    n


    .




    In this context, K is defined such that a ratio





    Lc
    K




    is a non-integer, and M is defined such that a ratio






    Lc
    ·
    M

    K




    is an integer.

    Tunneling Enabled Feedback FET
    93.
    发明公开

    公开(公告)号:US20240213321A1

    公开(公告)日:2024-06-27

    申请号:US18545730

    申请日:2023-12-19

    Applicant: IMEC VZW

    Inventor: Aryan Afzalian

    Abstract: Example embodiments relate to tunneling enabled feedback field effect transistors (FETs). One example system includes a feedback field effect transistor. The feedback field effect transistor includes a source region. The feedback field effect transistor also includes a channel region. Additionally, the feedback field effect transistor includes a drain region. Further, the feedback field effect transistor includes a gate. The channel region is between the source region and the drain region. The source region, the channel region, and the drain region include a semiconductor material with a bandgap that is smaller than 0.9 eV. The source region or the drain region has a dopant concentration that is smaller than 5×1019 cm−3. The gate is positioned along the channel and isolated from the channel.

    SENSING DEVICE AND A METHOD FOR DETECTION OF A CHARACTERISTIC OF A SUBSTANCE AT MULTIPLE TIME POINTS

    公开(公告)号:US20240210388A1

    公开(公告)日:2024-06-27

    申请号:US18392118

    申请日:2023-12-21

    Applicant: IMEC VZW

    CPC classification number: G01N33/5438 G01N33/54306

    Abstract: According to an aspect there is provided a sensing device for detection of at least one characteristic of a substance. The sensing device comprises:



    a plurality of cavities, each comprising an opening;
    a plurality of sensors for detecting the at least one characteristic, the plurality of sensors being arranged into a plurality of sets of sensors, each set being arranged in a mutually unique cavity;
    a plurality of protective membranes, each being arranged to cover the opening of the mutually unique cavity, preventing the substance from entering the cavity, thereby protecting the set of sensors from being exposed to the substance.




    The sensing device is configured for providing a different activation timing for different protective membranes, whereby different sets of sensors are exposed to the substance at different points in time, for providing detection of the at least one characteristic at multiple time points.

    Stacked SRAM Cell with a Dual-Side Interconnect Structure

    公开(公告)号:US20240206145A1

    公开(公告)日:2024-06-20

    申请号:US18545760

    申请日:2023-12-19

    CPC classification number: H10B10/125 H01L23/5286

    Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.

    ANALOG-TO-DIGITAL CONVERTER, ADC, A METHOD FOR CONTROLLING SAID ADC, AND A METHOD FOR CONTROLLING A DIGITAL-ANALOG-CONVERTER FOR SAID ADC

    公开(公告)号:US20240204794A1

    公开(公告)日:2024-06-20

    申请号:US18527683

    申请日:2023-12-04

    CPC classification number: H03M1/466

    Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises a comparator having a first input and a second input. The ADC further comprises a first digital-to-analog converter, DAC, and a second DAC configured to receive a first and a second digital reference signal, respectively. The digital reference signals (Dref) represent a signed binary value. The ADC is configured to compare input voltages (Vin), based on a first sampled input signal of a differential input signal and the first digital reference signal, and based on a second sampled input signal of the differential input signal and the second digital reference signal and, based on said comparison, adjust the reference voltage so as to approximate the differential input signal.

    Ultra-wideband Pulse and Ultra-wideband Pulse-based Ranging

    公开(公告)号:US20240201355A1

    公开(公告)日:2024-06-20

    申请号:US18538623

    申请日:2023-12-13

    CPC classification number: G01S11/08

    Abstract: A method for generating an ultra-wideband signal is provided. The method comprises the steps of generating at least one ultra-wideband pulse envelope comprising a main pulse and a precursor pulse, the precursor pulse being shorter in length and lower in amplitude compared to the main pulse, and modulating a carrier signal in amplitude such that the envelope corresponds to the at least one ultra-wideband pulse envelope and such that the carrier signal within the main pulse is phase-shifted with respect to the carrier signal within the precursor pulse.

    Method and System for Processing an Analog Signal

    公开(公告)号:US20240195445A1

    公开(公告)日:2024-06-13

    申请号:US18531318

    申请日:2023-12-06

    CPC classification number: H04B1/1027 H04B1/16

    Abstract: Example embodiments relate to methods and systems for processing analog signals. One example method for processing an analog signal includes modulating the analog signal using a chopping signal with a chopping frequency fchop to generate a modulated signal. The method also includes amplifying the modulated signal to generate an amplified signal. Additionally, the method includes low-pass filtering the amplified signal to generate a filtered signal that includes at least one harmonic of the modulated signal. Further, the method includes sub-sampling the filtered signal and performing a correlated double sampling operation by subtracting samples at the chopping frequency.

    System and Method for Joint Communication and Radar Sensing

    公开(公告)号:US20240192311A1

    公开(公告)日:2024-06-13

    申请号:US18531186

    申请日:2023-12-06

    CPC classification number: G01S7/0235 G01S7/006 H04W16/14

    Abstract: A system is provided for joint communication and radar sensing. The system includes at least one communication transmitter unit configured to transmit at least one communication pilot signal, at least one radar transmitter unit configured to transmit at least one radar pilot signal, a control unit configured to schedule the transmission of the at least one communication transmitter unit and/or the at least one radar transmitter unit using a time delay, and at least one receiver unit configured to receive the at least one radar pilot signal with the time delay with respect to the at least one communication pilot signal. A method of using the system for joint communication and radar sensing is also provided.

    STIMULATOR CIRCUIT, A SYSTEM FOR PROVIDING STIMULATION OF A BRAIN AND/OR NERVE AND A METHOD FOR PROVIDING A COMPENSATED STIMULATION SIGNAL

    公开(公告)号:US20240189593A1

    公开(公告)日:2024-06-13

    申请号:US18511762

    申请日:2023-11-16

    CPC classification number: A61N1/36034 A61N1/36025 A61N1/0456

    Abstract: A stimulator circuit comprises: a stimulation signal generating unit configured to generate a stimulation signal and provide the stimulation signal to an output wherein the stimulation signal is an alternating current, AC, signal having a sinusoidal-like waveform; and a compensation unit configured to generate a compensation current signal, wherein the compensation unit comprises a common mode voltage monitoring element configured to monitor a common mode voltage based on the stimulation signal, and a charge balancing element configured to generate the compensation current signal based on the common mode voltage; wherein the compensation unit is configured to provide the compensation current signal to the output for compensating an unbalanced charge of the stimulation signal and forming a compensated stimulation signal at the output.

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