公开(公告)号：US12113527B2

公开(公告)日：2024-10-08

申请号：US17886473

申请日：2022-08-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chang-Ting Wu

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0005 ,  H03K19/018557

Abstract: An off-chip driver (OCD), including a pull-up driver and a pull-down driver, is provided. The pull-up driver and the pull-down driver are coupled to an output pad. One of the pull-up driver and the pull-down driver includes a main driving circuit, an auxiliary driving circuit, a connection circuit, and a common impedance. The main driving circuit is used to perform an output driving operation on the output pad, and the auxiliary driving circuit is used to selectively perform the output driving operation on the output pad. A first terminal of the common impedance is coupled to a driving terminal of the main driving circuit and a driving terminal of the auxiliary driving circuit through the connection circuit. A second terminal of the common impedance is coupled to the output pad.

公开(公告)号：US20240332334A1

公开(公告)日：2024-10-03

申请号：US18736847

申请日：2024-06-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YU-HAN HSUEH

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469

Abstract: The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.

公开(公告)号：US20240331751A1

公开(公告)日：2024-10-03

申请号：US18193648

申请日：2023-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shu-Wei Yang

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093

Abstract: A data strobe latching circuit and an adjusting method for adjusting an internal write latency signal are provided. The DQS latching circuit includes a receiver, a counting circuit and a timing adjusting circuit. The receiver receives a DQS signal. The counting circuit counts at least one pulse of the DQS signal to generate an adjusting value. The timing adjusting circuit adjusts a timing of the internal write latency signal according to the adjusting value.

公开(公告)号：US20240329675A1

公开(公告)日：2024-10-03

申请号：US18190121

申请日：2023-03-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jia-Wun Syu

IPC: G05F1/46 ,  G05F1/575

CPC classification number: G05F1/468 ,  G05F1/461 ,  G05F1/575

Abstract: A startup circuit and a bandgap circuit are provided. The startup circuit includes a start referencing circuit and a driving circuit. The start referencing circuit is configured to receive an enabling signal ramping from a disabled voltage level to an enabled voltage level to generate a reference signal. The driving circuit has an input end coupled to the start referencing circuit and an output end coupled to an operational amplifier circuit of the bandgap circuit. The driving circuit is configured to generate a driving signal to the operational amplifier circuit according to the reference signal. The driving circuit comprises a plurality of buffer circuits coupled in series and at least one of the buffer circuits being a hysteresis buffer.

公开(公告)号：US12107002B2

公开(公告)日：2024-10-01

申请号：US18484452

申请日：2023-10-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC: H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US12100733B2

公开(公告)日：2024-09-24

申请号：US17465309

申请日：2021-09-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0607 ,  H01L29/0847

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

公开(公告)号：US12094517B2

公开(公告)日：2024-09-17

申请号：US17994397

申请日：2022-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Shuo Hsu

IPC: G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G11C11/4085

Abstract: A word line pump device of a dynamic random access memory (DRAM) chip and a clamp circuit thereof are provided. The DRAM chip receives a first voltage and a second voltage from outside, and the first voltage is smaller than the second voltage. The clamp circuit clamps a word line voltage to the second voltage in response to the word line pump device not receiving a power supply voltage.

公开(公告)号：US20240306369A1

公开(公告)日：2024-09-12

申请号：US18666835

申请日：2024-05-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu TSAI

IPC: H10B12/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/764 ,  H01L21/768 ,  H01L23/528 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/33 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a first vertical transistor and a second vertical transistor adjacent to the first vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The semiconductor device further includes a dielectric layer wrapping upper portions of the first word line and the second word line, and an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.

公开(公告)号：US12062656B2

公开(公告)日：2024-08-13

申请号：US17514507

申请日：2021-10-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/00 ,  H01L21/761 ,  H01L23/528 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L23/528 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

公开(公告)号：US20240268099A1

公开(公告)日：2024-08-08

申请号：US18164634

申请日：2023-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00 ,  H01L21/311 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762

Abstract: A semiconductor structure includes a semiconductor substrate, an isolation structure, and a conductive structure. The isolation structure is located on the semiconductor substrate. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface. The conductive structure has a trench. The trench extends to the second top surface and the lateral surface of the isolation structure. The conductive structure surrounds the isolation structure. The conductive structure is in contact with the first top surface of the isolation structure. A sidewall of a lower portion of the conductive structure is in contact with the isolation structure and extends beyond the second top surface of the isolation structure.