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91.发明授权公开(公告)号：US09183171B2
公开(公告)日：2015-11-10
申请号：US13631876
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Debendra Das Sharma , Robert G. Blankenship , Darren S. Jue
CPC classification number: G06F13/42 , G06F1/3253 , G06F13/38 , G06F13/382 , G06F13/4265 , Y02D10/14 , Y02D10/151
Abstract: Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.
Abstract translation: 描述了在退出低功率部分宽度高速链路状态时与快速偏移校正有关的方法和装置。 在一个实施例中，可以在第一时间点上传输有效车道上的出口飞行和/或空闲车道上的唤醒信号/序列，以使链路的一个或多个空闲车道进入活动状态。 在第二时间点（在第一时间点之后或之后），在链路的一个或多个空闲车道上发送训练序列。 并且，一个或多个空闲车道响应于训练序列而在第三时间点之前（在第二时间点之后或之后的其他时间）进行了偏斜校正。 还公开并要求保护其他实施例。
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公开(公告)号：US08806068B2
公开(公告)日：2014-08-12
申请号：US13706575
申请日：2012-12-06
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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公开(公告)号：US20250158738A1
公开(公告)日：2025-05-15
申请号：US18920362
申请日：2024-10-18
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Per E. Fornberg , Tal Israeli , Zuoguo Wu
Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.
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公开(公告)号：US12259835B2
公开(公告)日：2025-03-25
申请号：US17353416
申请日：2021-06-21
Applicant: Intel Corporation
Inventor： Debendra Das Sharma
IPC: G06F13/364 , G06F13/362 , G06F13/40 , G06F13/42
Abstract: An apparatus may comprise multiplexing circuitry to select an ingress lane from among a plurality of ingress lanes to couple to an egress lane; and retiming circuitry to retime a signal received on the selected ingress lane and transmit the retimed signal on the egress lane.
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公开(公告)号：US12219038B2
公开(公告)日：2025-02-04
申请号：US18462566
申请日：2023-09-07
Applicant: Intel Corporation
Inventor： Debendra Das Sharma
Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.
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Patent Agency Ranking
公开(公告)号：US20250013546A1
公开(公告)日：2025-01-09
申请号：US18794497
申请日：2024-08-05
Applicant: Intel Corporation
Inventor： Debendra Das Sharma
IPC: G06F11/263 , G06F11/10 , G06F11/22 , G06F11/30 , G06F13/40
Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.
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公开(公告)号：US12189470B2
公开(公告)日：2025-01-07
申请号：US17134240
申请日：2020-12-25
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Swadesh Choudhary
Abstract: Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.
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98.发明公开公开(公告)号：US20240345345A1
公开(公告)日：2024-10-17
申请号：US18757571
申请日：2024-06-28
Applicant: Intel Corporation
Inventor： Debendra Das Sharma
CPC classification number: G02B6/4274 , G02B6/43
Abstract: For example, an electronic system may include interconnect circuitry to communicate over an electrical interconnect; and a Physical layer (PHY) controller configured to access a plurality of optical-capability registers to identify optical-training control information and optical-capability information. For example, the optical-training control information may include a start-training bit. For example, based on a determination that the start-training bit is set to a predefined value, the PHY controller may initiate an optical-based link training procedure via the electrical interconnect to train a link between the electronic system and a partner electronic system over a redriver-based optical interconnect. For example, the optical-based link training procedure may be based on the optical-capability information.
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公开(公告)号：US20240329129A1
公开(公告)日：2024-10-03
申请号：US18537076
申请日：2023-12-12
Applicant: Intel Corporation
Inventor： Sridhar Muthrasanallur , Debendra Das Sharma , Swadesh Choudhary , Gerald Pasdast , Peter Onufryk
IPC: G01R31/317 , G06F11/27 , G06F13/42
CPC classification number: G01R31/31705 , G06F11/27 , G06F13/4221 , G06F2213/0026
Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
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公开(公告)号：US12099458B2
公开(公告)日：2024-09-24
申请号：US18056774
申请日：2022-11-18
Applicant: Intel Corporation
Inventor： Debendra Das Sharma
IPC: G06F13/40 , G06F12/1072 , G06F13/16 , G06F13/42 , G06F15/167
CPC classification number: G06F13/404 , G06F12/1072 , G06F13/1663 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F2212/1024 , G06F2212/1048
Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
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