TRANSMISSION
    92.
    发明申请
    TRANSMISSION 有权
    传输

    公开(公告)号:US20110034293A1

    公开(公告)日:2011-02-10

    申请号:US12744459

    申请日:2008-12-04

    Abstract: A transmission includes an input shaft (IP), an output shaft (OP), a single planetary gearset (SP), a compound planetary gearset (CP), shifting elements. The single planetary gearset is arranged before the compound planetary gearset, and the shifting elements comprise at least two brakes (B1,B2), the first clutch (C1), the second clutch (C2), the third clutch (C3), and all the shifting elements are positioned between the single planetary gearset and the compound planetary gearset, which has compact arrangements, and can reduce the power transmission length. The transmission also includes an one-way clutch (OWC) acted on the compound planetary gearset. When the transmission shifts to the first speed stage, the first clutch (C1) and the one-way clutch are operated, and the power is transferred from the input shaft to the output shaft via the single planetary gearset and the compound planetary gearset, and when the first speed stage is shifted to the second speed stage, only the first brake (B1) should be operated to engage, thereby it can reduce the frequency of operating the shifting elements and the shifting time in low speed stage.

    Abstract translation: 变速器包括输入轴(IP),输出轴(OP),单个行星齿轮组(SP),复合行星齿轮组(CP),变速元件。 单个行星齿轮组布置在复合行星齿轮组之前,变速元件包括至少两个制动器(B1,B2),第一离合器(C1),第二离合器(C2),第三离合器(C3)和所有 移动元件位于单个行星齿轮组和复合行星齿轮组之间,其具有紧凑的布置,并且可以降低动力传递长度。 变速器还包括作用在复合行星齿轮组上的单向离合器(OWC)。 当变速器移动到第一速度档时,第一离合器(C1)和单向离合器被操作,并且动力通过单个行星齿轮组和复合行星齿轮组从输入轴传递到输出轴,并且 当第一速度档位移动到第二速度档时,只有第一制动器(B1)应该被操作以啮合,从而可以降低在低速档中操作变速元件的频率和移动时间。

    HDLC hardware accelerator
    93.
    发明授权
    HDLC hardware accelerator 有权
    HDLC硬件加速器

    公开(公告)号:US07729322B2

    公开(公告)日:2010-06-01

    申请号:US10086576

    申请日:2002-02-28

    CPC classification number: H04L69/08 H04L69/16 H04L69/168 H04L69/324

    Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

    Abstract translation: HDLC加速器包括一个除帧和帧分频器,以分别加速PPP报文的去帧和成帧过程。 除法器包括输入接口单元,检测单元,转换单元和输出接口单元。 输入接口单元接收要解帧的数据包。 检测单元评估每个数据字节以检测特殊字节(例如,标志,转义和无效字节)。 转换单元通过删除标志和转义字节来去除所接收的数据,“去除”每个转义字节之后的数据字节,为每个标志字节提供标题字,并且基于帧校验序列(FCS)检查每个失真的分组, 值与数据包相关联。 输出接口单元提供去数据,并且可以在提供失真数据时进一步执行字节对齐。 状态控制单元提供指示要执行的特定任务的控制信号。

    Wireless multiprocessor system-on-chip with unified memory and fault inhibitor
    96.
    发明授权
    Wireless multiprocessor system-on-chip with unified memory and fault inhibitor 有权
    具有统一存储器和故障抑制器的无线多处理器片上系统

    公开(公告)号:US07450959B2

    公开(公告)日:2008-11-11

    申请号:US10841739

    申请日:2004-05-06

    CPC classification number: G06F21/554 G06F21/577 H04M1/72527

    Abstract: Wireless mobile communication device includes unified memory portion; processing units coupled with, and communicating through, unified memory; fault inhibitor coupled with unified memory inhibiting operational fault from nocent informon. Memory, fault inhibitor, and processing units fabricated on monolithic integrated circuit as system-on-chip disposed in wireless mobile personal host. Multiprocessor module includes fault inhibitor and applications and communications processing units and buses, coupled with unified memory. Integrated functional constituent can include coprocessor, accelerator, operational control unit, interprocessor controller, memory controller, bus management unit, bridge, arbiters, and transceiver. Method inhibits operational fault from nocent informon, setting device in operational or fallback state.

    Abstract translation: 无线移动通信设备包括统一存储器部分; 处理单元加上并通过统一记忆进行通信; 故障抑制器加上统一的记忆功能,禁止无效信息的操作故障。 存储器,故障抑制器和单片集成电路上制造的处理单元,作为芯片上系统布置在无线移动个人主机中。 多处理器模块包括故障抑制器和应用以及通信处理单元和总线,以及统一存储器。 集成功能组件可以包括协处理器,加速器,操作控制单元,处理器间控制器,存储器控制器,总线管理单元,桥接器,仲裁器和收发器。 方法禁止无效信号的操作故障,将设备设置为运行或后备状态。

    ELECTROPHORETIC MEDIUM AND PROCESS FOR THE PRODUCTION THEREOF
    97.
    发明申请
    ELECTROPHORETIC MEDIUM AND PROCESS FOR THE PRODUCTION THEREOF 有权
    电泳介质及其生产工艺

    公开(公告)号:US20080264791A1

    公开(公告)日:2008-10-30

    申请号:US12167290

    申请日:2008-07-03

    CPC classification number: G02F1/167

    Abstract: A two-phase electrophoretic medium comprises a continuous phase and a discontinuous phase. The discontinuous phase comprises a plurality of droplets, each of which comprises a suspending fluid and at least one particle disposed within the suspending fluid and capable of moving through the fluid upon application of an electric field to the electrophoretic medium. The continuous phase surrounds and encapsulates the discontinuous phase. To reduce the humidity sensitivity of the medium, a non-ionizable or crystalline polymer may be used as the continuous phase.

    Abstract translation: 两相电泳介质包括连续相和不连续相。 不连续相包括多个液滴,每个液滴包括悬浮流体和设置在悬浮流体内的至少一个颗粒,并且在向电泳介质施加电场时能够移动通过流体。 连续相围绕并封装不连续相。 为了降低介质的湿度敏感性,可以使用不可离子化或结晶的聚合物作为连续相。

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