公开(公告)号：US11829650B2

公开(公告)日：2023-11-28

申请号：US18103857

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US11726908B2

公开(公告)日：2023-08-15

申请号：US17672872

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Tracy D. Evans ,  Tomoko Ogura Iwasaki ,  Avani F. Trivedi ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/0882 ,  G06F1/3212 ,  G06F11/30 ,  G06F11/07 ,  G06F12/0831

CPC classification number: G06F12/0253 ,  G06F1/3212 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0833 ,  G06F12/0882

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

公开(公告)号：US11698742B2

公开(公告)日：2023-07-11

申请号：US17673408

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Aparna U. Limaye ,  Avani F. Trivedi ,  Tomoko Ogura Iwasaki ,  Tracy D. Evans

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/34 ,  G11C16/24 ,  G11C16/04

CPC classification number: G06F3/0647 ,  G06F3/0608 ,  G06F3/0673 ,  G06F12/10 ,  G11C16/24 ,  G11C16/3459 ,  G06F2212/1044 ,  G06F2212/657 ,  G11C16/0483

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.

公开(公告)号：US20230205629A1

公开(公告)日：2023-06-29

申请号：US18117555

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F3/0679 ,  G06F3/064 ,  G06F3/0649 ,  G06F3/0619

Abstract: An apparatus can include a media management superblock component. The media management superblock component can determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component can compare the quantity of bad blocks to a bad block criteria. The media management superblock component can write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

公开(公告)号：US20230195356A1

公开(公告)日：2023-06-22

申请号：US17555160

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

公开(公告)号：US11663148B2

公开(公告)日：2023-05-30

申请号：US17138082

申请日：2020-12-30

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jianmin Huang

IPC: G06F13/24 ,  G06F13/16 ,  G06F12/0868 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/24

Abstract: Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

公开(公告)号：US11579996B2

公开(公告)日：2023-02-14

申请号：US17692777

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/00 ,  G06F11/30 ,  G11C29/02 ,  G06F12/14 ,  G11C16/14 ,  G06F11/07 ,  G06F11/34

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

公开(公告)号：US20220357863A1

公开(公告)日：2022-11-10

申请号：US17870320

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

公开(公告)号：US11409661B2

公开(公告)日：2022-08-09

申请号：US16996329

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F12/1009 ,  G06F11/10

Abstract: A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both.

公开(公告)号：US20220199189A1

公开(公告)日：2022-06-23

申请号：US17393886

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Jung Sheng Hoei ,  Jianmin Huang ,  Ashutosh Malshe ,  Xiangang Luo

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/40

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).