公开(公告)号：US20190214366A1

公开(公告)日：2019-07-11

申请号：US15867577

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/13026 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US10332844B2

公开(公告)日：2019-06-25

申请号：US15717956

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L21/00 ,  H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A manufacturing method of a packaging structure is provided. First, a carrier is provided. A conductive layer is formed on the carrier. A conductive frame is formed on the conductive layer. The conductive frame is in contact with and electrically connected to the conductive layer. A chip is placed on the conductive layer. The conductive frame surrounds the chip. An insulation encapsulation is formed to encapsulate the chip, and the insulation encapsulation exposes an active surface of the chip. A redistribution layer is formed on the active surface of the chip. The redistribution layer extends from the active surface to the insulation encapsulation.

公开(公告)号：US20190164948A1

公开(公告)日：2019-05-30

申请号：US16112785

申请日：2018-08-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module includes a protection layer and a plurality of conductive bars embedded in the protection layer. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US10276526B2

公开(公告)日：2019-04-30

申请号：US16162389

申请日：2018-10-17

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/50 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US20190057931A1

公开(公告)日：2019-02-21

申请号：US15680176

申请日：2017-08-17

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/498 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block.

公开(公告)号：US20190051625A1

公开(公告)日：2019-02-14

申请号：US16162389

申请日：2018-10-17

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/50 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US10177011B2

公开(公告)日：2019-01-08

申请号：US15603475

申请日：2017-05-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.

公开(公告)号：US20180374717A1

公开(公告)日：2018-12-27

申请号：US15630972

申请日：2017-06-23

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552

Abstract: An adhesive layer is formed on a semiconductor wafer. The semiconductor wafer is diced to form a plurality of chips. Each of the chips has an adhesive sheet diced from the adhesive layer. Adhesive sheets of the chips are adhered to a carrier. The chips and the carrier are encapsulated by a mold layer. The mold layer is grinded to form a grinded surface. An interconnection structure is formed on the grinded surface. A plurality of semiconductor packages are formed by sawing the mold layer and at least a polyimide layer of the interconnection structure.

公开(公告)号：US10141276B2

公开(公告)日：2018-11-27

申请号：US15599481

申请日：2017-05-19

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US20180114781A1

公开(公告)日：2018-04-26

申请号：US15717944

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/50 ,  H01L23/49 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.