中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

115 records (took 0.03 seconds)

    OPEN BLOCK READ ICC REDUCTION
    92.
    发明公开
    OPEN BLOCK READ ICC REDUCTION 审中-公开

    公开(公告)号：US20240290395A1

    公开(公告)日：2024-08-29

    申请号：US18360634

    申请日：2023-07-27

    Applicant: SanDisk Technologies LLC

    Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Deepanshu Dutta

    IPC: G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/28 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24

    Abstract: Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

    NON-VOLATILE MEMORY WTH LOOP DEPENDANT RAMP-UP RATE
    94.
    发明公开
    NON-VOLATILE MEMORY WTH LOOP DEPENDANT RAMP-UP RATE 审中-公开

    公开(公告)号：US20240233826A1

    公开(公告)日：2024-07-11

    申请号：US18357339

    申请日：2023-07-24

    Applicant: SanDisk Technologies LLC

    Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

    IPC: G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/3459

    Abstract: A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines. To reduce the amount of current used, the memory system includes a loop dependent reduction in the ramp-up rate of the overdrive voltage applied to unselected word lines during program-verify.

    EARLY PROGRAM TERMINATION WITH ADAPTIVE TEMPERATURE COMPENSATION
    95.
    发明公开
    EARLY PROGRAM TERMINATION WITH ADAPTIVE TEMPERATURE COMPENSATION 审中-公开

    公开(公告)号：US20240168661A1

    公开(公告)日：2024-05-23

    申请号：US18355337

    申请日：2023-07-19

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Yihang Liu ,  Jiahui Yuan

    IPC: G06F3/06 ,  G11C29/12

    CPC classification number: G06F3/0629 ,  G06F3/0619 ,  G06F3/0679 ,  G11C29/12005 ,  G11C2029/1202

    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

    NON-VOLATILE MEMORY WITH PROGRAMMABLE RESISTANCE NON-DATA WORD LINE
    97.
    发明公开
    NON-VOLATILE MEMORY WITH PROGRAMMABLE RESISTANCE NON-DATA WORD LINE 审中-公开

    公开(公告)号：US20240103742A1

    公开(公告)日：2024-03-28

    申请号：US17955018

    申请日：2022-09-28

    Applicant: SanDisk Technologies LLC

    Inventor： Towhidur Razzak ,  Ravi Kumar ,  Abu Naser Zainuddin ,  Jiahui Yuan

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

    Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.

Patent Agency Ranking