公开(公告)号：US07403040B2

公开(公告)日：2008-07-22

申请号：US11790014

申请日：2007-04-23

Applicant: Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/017545

Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

Abstract translation: 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US20080019451A1

公开(公告)日：2008-01-24

申请号：US11863604

申请日：2007-09-28

Applicant: Seong-Jin Jang ,  Jeong-Don Lim

Inventor： Seong-Jin Jang ,  Jeong-Don Lim

IPC: H04L27/00

CPC classification number: G11C7/1006 ,  G06F7/501 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C2207/108

Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.

Abstract translation: 数据总线反转（DBI）电路包括至少一个DBI块，其被配置为基于输入数据位的逻辑状态反转输入数据信号。 DBI块包括比较判定单元，该比较判定单元被配置为通过比较输入数据信号和先前输入数据信号的各个比特信号，在第一模式中，基于改变的比特数来生成比较信号。 比较判定单元生成控制输入数据是否反转的反转控制信号。 在第二模式中，比较判定单元根据输入数据信号位的主要逻辑状态生成反转控制信号。 数据转换单元被配置为响应于反转控制信号来反转输入数据信号。 还公开了方法实施例。

公开(公告)号：US20070297552A1

公开(公告)日：2007-12-27

申请号：US11812438

申请日：2007-06-19

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC: H04L7/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

Abstract translation: 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。

公开(公告)号：US07269699B2

公开(公告)日：2007-09-11

申请号：US10733413

申请日：2003-12-12

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G06F12/00 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

Abstract translation: 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

公开(公告)号：US20070115751A1

公开(公告)日：2007-05-24

申请号：US11594807

申请日：2006-11-09

Applicant: Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号中的一个来输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20070069788A1

公开(公告)日：2007-03-29

申请号：US11519252

申请日：2006-09-12

Applicant: Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

Inventor： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

IPC: H03K3/00

CPC classification number: G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356156

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract translation: 半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。 第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。 因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。

公开(公告)号：US20070025164A1

公开(公告)日：2007-02-01

申请号：US11453518

申请日：2006-06-15

Applicant: Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

Inventor： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

IPC: G11C7/00

CPC classification number: G11C5/145

Abstract: A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

Abstract translation: 一种用于半导体存储器件的电压产生电路。 电压产生电路包括用于升高电源电压的多升压单元，连接到多升压单元的最终升压节点的输出晶体管和输出节点，以及与最终的电连接电连接的电荷共享元件 所述传输晶体管的升压节点和栅极节点在所述周期的至少一部分期间被使能，所述多个升压单元对所述电源电压进行升压，并且在所述最终升压节点和所述转移的所述栅极节点之间执行电荷共享 晶体管。

公开(公告)号：US20060224814A1

公开(公告)日：2006-10-05

申请号：US11358798

申请日：2006-02-21

Applicant: Sung-Hoon Kim ,  Seong-Jin Jang ,  Su-Jin Park

Inventor： Sung-Hoon Kim ,  Seong-Jin Jang ,  Su-Jin Park

IPC: G06F12/06

CPC classification number: G11C7/22

Abstract: A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.

Abstract translation: 半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。 第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。 第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1） 响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。 还讨论了相关方法。

公开(公告)号：US20060062286A1

公开(公告)日：2006-03-23

申请号：US11128795

申请日：2005-05-13

Applicant: Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

Inventor： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC: H04B1/38

CPC classification number: G11C7/1072 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

Abstract: For data training in a memory device, a selecting unit selects a subset of data bit patterns received from a controlling device. In addition, a storing unit comprised of memory cells of the memory device stores the selected subset of data bit patterns. Such stored data bit patterns are then sent back to the controlling device that determines the level of data skew. Such data training more accurately reflects the actual paths and environments of the transmitted data bits.

Abstract translation: 对于存储器件中的数据训练，选择单元选择从控制装置接收的数据位模式的子集。 此外，由存储器件的存储器单元组成的存储单元存储所选择的数据位模式子集。 然后将这种存储的数据位模式发送回确定数据偏移水平的控制设备。 这种数据训练更准确地反映了传输数据位的实际路径和环境。

公开(公告)号：US06894946B2

公开(公告)日：2005-05-17

申请号：US10377374

申请日：2003-02-28

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C8/00 ,  G06F12/00 ,  G11C11/00 ,  H03B19/00 ,  H03L7/00

CPC classification number: G11C29/028 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/104 ,  G11C2207/2254

Abstract: A memory system includes a memory device that includes an active termination circuit. The memory system further includes a controller circuit that includes a frequency control circuit that is configured to modulate a system clock between a first frequency value and a second frequency value, greater than the first frequency value, responsive to a control signal. The controller circuit is further configured to determine an active termination value for the active termination circuit responsive to the system clock at the first frequency value, and to apply commands to the memory device responsive to the system clock at the second frequency value.

Abstract translation: 存储器系统包括包括有源终端电路的存储器件。 存储器系统还包括控制器电路，其包括频率控制电路，其被配置为响应于控制信号，调制大于第一频率值的第一频率值和第二频率值之间的系统时钟。 控制器电路还被配置为响应于处于第一频率值的系统时钟来确定有效终端电路的有效终止值，并且响应于系统时钟以第二频率值将命令应用于存储器件。