公开(公告)号：US20210296295A1

公开(公告)日：2021-09-23

申请号：US17337752

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kong-Toon Ng ,  Hung-Ho Lee ,  Chee-Key Chung ,  Chang-Fu Lin ,  Chi-Hsin Chiu

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

公开(公告)号：US20210287962A1

公开(公告)日：2021-09-16

申请号：US16872740

申请日：2020-05-12

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

IPC: H01L23/433 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

公开(公告)号：US20200350261A1

公开(公告)日：2020-11-05

申请号：US16875240

申请日：2020-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chang-Fu Lin ,  Chun-Tang Lin ,  Bo-Hao Chang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.

公开(公告)号：US20200258871A1

公开(公告)日：2020-08-13

申请号：US16856259

申请日：2020-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Han-Hung Chen ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Rung-Jeng Lin ,  Fu-Tang Huang

IPC: H01L25/10 ,  H01L25/00

Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

公开(公告)号：US10600708B2

公开(公告)日：2020-03-24

申请号：US16170904

申请日：2018-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Shan Tsai ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.

公开(公告)号：US20200091059A1

公开(公告)日：2020-03-19

申请号：US16690801

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US10522453B2

公开(公告)日：2019-12-31

申请号：US15352856

申请日：2016-11-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US10510720B2

公开(公告)日：2019-12-17

申请号：US15372638

申请日：2016-12-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Kuo-Hua Yu ,  Fu-Tang Huang

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US20190273321A1

公开(公告)日：2019-09-05

申请号：US15993243

申请日：2018-05-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Han-Hung Chen ,  Chun-Yi Huang ,  Chang-Fu Lin ,  Rung-Jeng Lin ,  Kuo-Hua Yu

IPC: H01Q9/04 ,  H05K1/14 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/36 ,  H01Q1/22

Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.

公开(公告)号：US20190057917A1

公开(公告)日：2019-02-21

申请号：US15860222

申请日：2018-01-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Shan Tsai ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package and a method of fabricating the same are provided. The method includes disposing an electronic component on a first side of an interposer, forming a first encapsulant on the first side of the interposer to encapsulate the electronic component, forming a plurality of conductive elements on a second side of the interposer, and forming a second encapsulant on the second side of the interposer to encapsulate the conductive elements. During thermal cycling of the electronic package, shrinkage forces of the first encapsulant and the second encapsulant can offset each other so as to mitigate warping of the interposer.