公开(公告)号：US20090119540A1

公开(公告)日：2009-05-07

申请号：US11666260

申请日：2005-10-25

Applicant: Reinhard Weiberle ,  Bernd Mueller ,  Yorck Collani ,  Rainer Gmehlich ,  Eberhard Boehl

Inventor： Reinhard Weiberle ,  Bernd Mueller ,  Yorck Collani ,  Rainer Gmehlich ,  Eberhard Boehl

IPC: G06F11/16

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F11/1695 ,  G06F2201/845

Abstract: A device and method for performing switchover operations in a computer system having at least two execution units, a changeover switch being provided which switches between at least two operating modes, a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, in addition, a comparator being provided which is activated in the comparison mode, in which an arrangement provides desired switchover detection, the arrangement for desired switchover detection controlling the changeover switch in order to switch from one operating mode to another.

Abstract translation: 一种用于在具有至少两个执行单元的计算机系统中执行切换操作的装置和方法，提供了切换开关，所述切换开关在至少两个操作模式之间切换，对应于比较模式的第一操作模式和对应于 一种性能模式，此外，提供在比较模式中被激活的比较器，其中布置提供期望的切换检测，控制转换开关的所需切换检测的布置以便从一种操作模式切换到另一操作模式。

公开(公告)号：US20090031115A1

公开(公告)日：2009-01-29

申请号：US12138741

申请日：2008-06-13

Applicant: Jay R. Pruiett ,  Gregory R. Sykes ,  Timothy D. Skutt

Inventor： Jay R. Pruiett ,  Gregory R. Sykes ,  Timothy D. Skutt

IPC: G06F9/30

CPC classification number: G06F11/1641 ,  G06F11/1687 ,  G06F2201/845

Abstract: A method of providing high integrity checking for an N-lane computer processing module (Module), N being an integer greater than equal to two. The method comprises the steps of: detecting, by a data Output Management unit (OM), when any of the N processing lanes sends different output data; configuring each Hosted Application as either normal or high integrity; for the Hosted Applications configured as high integrity, running an identical version of the software source code targeted for similar or dissimilar microprocessors on all N processing lanes, and activating a Time Management Unit, Critical Regions Management Unit, data Input Management Unit and data Output Management Unit for each of the N processing lanes; and for the Hosted Applications configured as normal integrity, running a copy of the software on one of the N processing lanes, and not activating the Time Management Unit, Critical Regions Management Unit, Input Management Unit and Output Management Unit for the one activated processing lane while that Hosted Application is running.

Abstract translation: 一种为N通道计算机处理模块（Module）提供高完整性检查的方法，N为大于等于2的整数。 该方法包括以下步骤：当数据输出管理单元（OM）检测任何N个处理通道发送不同的输出数据时; 将每个托管应用程序配置为正常或高完整性; 对于配置为高完整性的托管应用程序，在所有N个处理通道上运行相同或不同微处理器的相同版本的软件源代码，并激活时间管理单元，关键区域管理单元，数据输入管理单元和数据输出管理 每个N个加工车道的单位; 并且对于配置为正常完整性的托管应用，在N个处理通道之一上运行软件的副本，并且不激活一个激活的处理通道的时间管理单元，关键区域管理单元，输入管理单元和输出管理单元 而托管应用程序正在运行。

公开(公告)号：US20090024908A1

公开(公告)日：2009-01-22

申请号：US11659308

申请日：2005-08-01

Applicant: Thomas Kottke ,  Andreas Steininger ,  Christian El Salloum

Inventor： Thomas Kottke ,  Andreas Steininger ,  Christian El Salloum

IPC: G06F11/07

CPC classification number: G06F11/1679 ,  G06F11/0739 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/0796 ,  G06F2201/845

Abstract: A method for error registration and a register which is assigned to a dual-computer system, information in the form of bits being stored in the register, the dual-computer system including an error-detection mechanism, and the bits in the register as error bits representing at least one error signal of the error-detection mechanism.

Abstract translation: 一种用于错误注册的方法和分配给双计算机系统的寄存器，以比特形式存储在寄存器中的信息，双计算机系统包括错误检测机制，并且寄存器中的位作为错误 表示错误检测机构的至少一个误差信号的位。

公开(公告)号：US20080263340A1

公开(公告)日：2008-10-23

申请号：US11666403

申请日：2005-10-25

Applicant: Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich ,  Eberhard Boehl

Inventor： Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich ,  Eberhard Boehl

IPC: G06F9/318

CPC classification number: G06F11/1641 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1683 ,  G06F2201/845

Abstract: A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, characterized in that, in the computer system, a mode signal and/or changes in the mode signal, which are indicative of the current operating mode, are generated, and at least the changes in the mode signal and/or this mode signal itself are made available outside of the computer system for analysis purposes.

Abstract translation: 一种用于分析来自具有至少两个执行单元的计算机系统的信号的方法和装置，在所述计算机系统中，在至少两个操作模式之间执行切换操作，以及对应于比较模式的第一操作模式和第二操作模式 模式，其特征在于，在计算机系统中，生成表示当前操作模式的模式信号和/或模式信号的改变，并且至少模式信号和 /或该模式信号本身在计算机系统外部可用于分析目的。

公开(公告)号：US20080126718A1

公开(公告)日：2008-05-29

申请号：US11666407

申请日：2005-10-25

Applicant: Thomas Kottke ,  Stefan Trittler

Inventor： Thomas Kottke ,  Stefan Trittler

IPC: G06F12/00

CPC classification number: G06F11/1695 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/1641 ,  G06F2201/845

Abstract: A method and device for monitoring a memory unit in a system including at least two processing units, a switchover arrangement being included that allows switching between at least two operating modes of the system, the device being arranged to log the memory content and/or the operating mode in which the memory content was generated.

Abstract translation: 一种用于监视包括至少两个处理单元的系统中的存储器单元的方法和设备，包括允许在所述系统的至少两个操作模式之间切换的切换装置，所述设备被布置为记录存储器内容和/或 生成内存内容的操作模式。

公开(公告)号：US20070277023A1

公开(公告)日：2007-11-29

申请号：US10560962

申请日：2004-06-22

Applicant: Reinhard Weiberle ,  Bernd Mueller ,  Ralf Angerbauer ,  Rainer Gmehlich ,  Stefan Benz

Inventor： Reinhard Weiberle ,  Bernd Mueller ,  Ralf Angerbauer ,  Rainer Gmehlich ,  Stefan Benz

IPC: G06F9/00

CPC classification number: G06F11/1641 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/165 ,  G06F2201/845

Abstract: A method for switching over between at least two operating modes of a processor unit, having at least two execution units is provided, in which method a change from a first operating mode to a second operating mode is triggered by the processor unit accessing a predefined memory address.

Abstract translation: 提供了一种用于在具有至少两个执行单元的处理器单元的至少两个操作模式之间进行切换的方法，其中，从处理器单元访问预定存储器触发从第一操作模式到第二操作模式的改变 地址。

公开(公告)号：US07287185B2

公开(公告)日：2007-10-23

申请号：US10819241

申请日：2004-04-06

Applicant: Kevin David Safford ,  Donald Charles Soltis, Jr.

Inventor： Kevin David Safford ,  Donald Charles Soltis, Jr.

IPC: G06F11/00

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3851 ,  G06F11/1629 ,  G06F2201/845

Abstract: In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.

Abstract translation: 在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组， 可靠的运行模式。 电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则以非高可靠性操作模式执行第一指令组。

公开(公告)号：US07237144B2

公开(公告)日：2007-06-26

申请号：US10818994

申请日：2004-04-06

Applicant: Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Eric Richard Delano

Inventor： Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Eric Richard Delano

IPC: G06F11/00

CPC classification number: G06F11/1641 ,  G06F11/1625 ,  G06F2201/845

Abstract: A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.

Abstract translation: 提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与 第二输出信号。

公开(公告)号：US07114095B2

公开(公告)日：2006-09-26

申请号：US10157890

申请日：2002-05-31

Applicant: Dejan S. Milojicic ,  Alan Messer

Inventor： Dejan S. Milojicic ,  Alan Messer

IPC: G06F11/00

CPC classification number: G06F9/3885 ,  G06F11/20 ,  G06F11/2038 ,  G06F2201/845

Abstract: A system for switching between computer hardware configurations is provided. The system may include multiple processors and an operating system that facilitates switching between a lock step or fail-over processing operation configuration and a multiprocessor operation configuration.

公开(公告)号：US07085959B2

公开(公告)日：2006-08-01

申请号：US10187833

申请日：2002-07-03

Applicant: Kevin David Safford

Inventor： Kevin David Safford

IPC: G06F11/00

CPC classification number: G06F11/2038 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/2025 ,  G06F2201/845

Abstract: An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

Abstract translation: 在多处理器计算机系统中，使用以先进的多核处理器架构运行的装置和相应的方法来增强从锁定步骤的丢失中的恢复。 用于从失锁步骤恢复的装置包括在计算机系统中操作的多个处理器单元，每个处理器单元具有以锁定步骤操作的至少两个处理器单元，以及以锁定步骤操作的至少一个空闲处理器单元; 以及耦合到处于锁定步骤的两个处理器单元和空闲处理器单元的控制器。 控制器包括用于将两个锁步骤处理器单元中的每一个的架构状态复制到空闲处理器单元的机构。