公开(公告)号：US09929087B2

公开(公告)日：2018-03-27

申请号：US15098894

申请日：2016-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Pen Guo ,  Ming-Hsien Lin

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L27/02 ,  H01L27/118 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L23/5228 ,  H01L23/53204 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/0607 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the second conductor is oriented along a second direction generally perpendicular to the first direction, and the second conductor is electrically connected to the first conductor. The IC further comprises a third conductor in another layer of the IC, oriented along the second direction, and above the second conductor; a first via connecting the first and third conductors; and a second via connecting the second and third conductors.

公开(公告)号：US20180082945A1

公开(公告)日：2018-03-22

申请号：US15444933

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih -Chao Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: Conductive contacts include a first conductor disposed within a first dielectric layer, the first conductor having a recessed area in least one surface. A second dielectric layer is formed over the first dielectric layer, comprising a trench positioned over the first conductor. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.

公开(公告)号：US09917048B2

公开(公告)日：2018-03-13

申请号：US14856358

申请日：2015-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

公开(公告)号：US09881798B1

公开(公告)日：2018-01-30

申请号：US15215544

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L21/283 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28 ,  H01L23/522

CPC classification number: H01L23/53204 ,  H01L21/02697 ,  H01L21/28 ,  H01L21/283 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L33/48

Abstract: A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects.

公开(公告)号：US09576867B2

公开(公告)日：2017-02-21

申请号：US15093528

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/48 ,  H01L21/66 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US09502353B2

公开(公告)日：2016-11-22

申请号：US14310612

申请日：2014-06-20

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Kenichi Watanabe

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

公开(公告)号：US09406613B2

公开(公告)日：2016-08-02

申请号：US14313010

申请日：2014-06-24

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Kenichi Watanabe

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06 ,  H01L23/528 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

公开(公告)号：US09355898B2

公开(公告)日：2016-05-31

申请号：US14447399

申请日：2014-07-30

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Houssam Wafic Jomaa ,  David Fraser Rae ,  Layal Rouhana ,  Omar James Bchir

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/495 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

公开(公告)号：US09343424B2

公开(公告)日：2016-05-17

申请号：US14730327

申请日：2015-06-04

Applicant: Wistron Corporation

Inventor： Hui-Ying Chou ,  Lee-Chieh Kang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/02 ,  H01L23/12 ,  H01L23/00 ,  H01L23/13 ,  H05K3/00 ,  H01L23/528 ,  H01L23/532 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/528 ,  H01L23/53204 ,  H05K3/0005 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.

Abstract translation: 提供了一种形成对应于SMT部件的焊盘的空隙的方法。 该方法包括以下步骤：将一个或多个条件参数输入到搜索单元。 参考条件参数，搜索单元搜索所有的焊盘，以获得预选的焊盘组。 提供判断单元以确定预先选择的焊盘组中的每个焊盘是否满足预定的处理要求以生成要处理的焊盘组。 执行单元参照要处理的一组焊盘的角坐标来执行空隙形成步骤，以便在与焊盘的角部相对应的接触表面的部分处形成至少一个空隙。 在一个实施例中，相应地在接触表面处形成与被处理组的每个焊盘的各个角相关的四个空隙。