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公开(公告)号：US20130278453A1
公开(公告)日：2013-10-24
申请号：US13553092
申请日：2012-07-19
Applicant: Jesper STEENSGAARD-MADSEN
Inventor： Jesper STEENSGAARD-MADSEN
CPC classification number: H03M1/201 , H03M1/0641 , H03M1/0668 , H03M1/462 , H03M1/468
Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.
Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。
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92.发明授权公开(公告)号：US08416108B2
公开(公告)日：2013-04-09
申请号：US13161994
申请日：2011-06-16
Applicant: Masato Nakada
Inventor： Masato Nakada
IPC: H03M1/20
CPC classification number: H03M1/201
Abstract: An AD conversion apparatus includes a shift signal generating portion configured to generate n shift signals (n is a natural number greater than one) of which amplitudes are different from each other; a shift signal controlling portion configured to control the shift signal generating portion; a compounding portion configured to compound input analog signal and the n shift signals sequentially into n first signals; an AD converting portion configured to execute AD conversion to convert the n first signals into n second signals; and a signal processing portion configured to calculate an average of the n second signals to generate output digital signal.
Abstract translation: AD转换装置包括：移位信号产生部分，被配置为产生振幅彼此不同的n个移位信号（n是大于1的自然数）; 移位信号控制部，被配置为控制所述移位信号生成部; 复合部，被配置为将输入模拟信号和所述n个移位信号顺序地复合成n个第一信号; AD转换部分，被配置为执行AD转换以将n个第一信号转换为n个第二信号; 以及信号处理部，被配置为计算所述n个第二信号的平均值以产生输出数字信号。
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公开(公告)号：US20130082853A1
公开(公告)日：2013-04-04
申请号：US13251935
申请日：2011-10-03
Applicant: Khurram MUHAMMAD , Tajinder Manku , Semyon Lebedev
Inventor： Khurram MUHAMMAD , Tajinder Manku , Semyon Lebedev
Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.
Abstract translation: 公开了一种数模转换器。 该转换器包括梯度校正模块，该梯度校正模块基于梯度误差的模型产生校正项。 然后将校正项应用于数字域中的信号路径或应用于模拟域中的数模转换器的输出。 用于产生校正项的模型基于当前源元素阵列中的垂直梯度误差，其可以使用二阶多项式来建模和校准。 此外，公开了具有奈奎斯特DAC和过采样DAC的数模转换器。 当使能过采样DAC时，可能会增加奈奎斯特DAC的分辨率，同时降低转换速率。
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94.发明授权公开(公告)号：US08384578B2
公开(公告)日：2013-02-26
申请号：US13192056
申请日：2011-07-27
Applicant: Bob Verbruggen , Jan Craninckx
Inventor： Bob Verbruggen , Jan Craninckx
Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.
Abstract translation: 描述了用于接收模拟输入信号并输出所述模拟输入信号的数字表示的模拟（A / D）转换器电路。 A / D转换器电路包括：第一转换器级，被配置为接收模拟输入信号并产生第一组转换位，第一完成信号和表示模拟输入信号与信号之间的差的残留模拟输出信号 由所述第一组转换位表示的第二转换器级，包括布置成用于接收第一完成信号并用于产生时钟信号的时钟产生电路，多个比较器被配置为用于接收残留模拟输出信号和公共参考 电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定;数字处理级，被配置用于接收多个比较器判决并用于产生第二组转换位，用于产生数字 通过组合第一个a来表示模拟输入信号 第二组转换位。
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公开(公告)号：US07956778B2
公开(公告)日：2011-06-07
申请号：US12656490
申请日：2010-02-01
Applicant: Tetsuhiro Koyama
Inventor： Tetsuhiro Koyama
IPC: H03M1/66
Abstract: There is provided an analog-to-digital converter capable of performing analog-to-digital conversion with good accuracy. The analog-to-digital converter in accordance with the present invention includes a dither generation circuit 11 which generates dither; an input polarity switching unit 1 which switches a polarity of an input signal; an integrator 2; an integrator output regulator circuit 5 which regulates an output voltage of the integrator 2; a window comparator 3; a control circuit 4 which uses the comparison result of the window comparator 3 to control the input polarity switching unit 1, the integrator output regulator circuit 5, and the window comparator 3 as well as to generate a digital signal. The dither generation circuit 11 generates dither in such a manner that a cycle in which the digital signal is read is an integral multiple of a dither cycle. Further, the dither generation circuit 11 generates dither in such a manner that the number of times the count value is generated in the first half of one cycle of the dither is different from the number of times the count value is generated in the second half cycle thereof.
Abstract translation: 提供了能够以高精度执行模数转换的模数转换器。 根据本发明的模拟 - 数字转换器包括产生抖动的抖动产生电路11; 输入极性切换单元1，其切换输入信号的极性; 积分器2; 积分器输出调节器电路5，其调节积分器2的输出电压; 窗口比较器3; 使用窗口比较器3的比较结果来控制输入极性切换单元1，积分器输出调节器电路5和窗口比较器3以及生成数字信号的控制电路4。 抖动产生电路11产生抖动，使得读取数字信号的周期是抖动周期的整数倍。 此外，抖动发生电路11产生抖动，使得在抖动的一个周期的前半部分中产生计数值的次数与在第二个半周期中产生计数值的次数不同 其中。
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Patent Agency Ranking
公开(公告)号：US20080231485A1
公开(公告)日：2008-09-25
申请号：US11689377
申请日：2007-03-21
Applicant: Matthew P. Newlin , Lee K. Strandjord , Thomas C. Greening , Gregory W. Keith
Inventor： Matthew P. Newlin , Lee K. Strandjord , Thomas C. Greening , Gregory W. Keith
IPC: H03M1/20
CPC classification number: H03M1/0641 , G06F7/588 , H03M1/201 , H03M1/661
Abstract: Systems and methods for improving efficiency of a data converter. An example method generates a noise signal, alters the spectrum of the noise signal based on operation of an associated data converter, and supplies the altered spectrum noise signal to the associated data converter. The data converter is a digital-to-analog converter or an analog-to-digital converter. The altered spectrum noise signal is notched at frequencies of interest. The spectrum is altered by sending a signal generated by a random number generator to a delay device and adding the output of the delay device from the output of the random number generator. Also, the spectrum is altered by seeding first and second identical random number generators, delaying the operation of the first random number generator, and adding the output of the delayed first random number generator from the second random number generator.
Abstract translation: 提高数据转换器效率的系统和方法。 示例性方法产生噪声信号，基于相关联的数据转换器的操作改变噪声信号的频谱，并将改变的频谱噪声信号提供给相关联的数据转换器。 数据转换器是数模转换器或模数转换器。 改变的频谱噪声信号在感兴趣的频率处被切断。 通过将随机数发生器产生的信号发送到延迟装置并且从随机数发生器的输出添加延迟装置的输出来改变频谱。 此外，通过播种第一和第二相同的随机数发生器来改变频谱，延迟第一随机数发生器的操作，以及将来自第二随机数发生器的延迟的第一随机数发生器的输出相加。
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公开(公告)号：US06331831B1
公开(公告)日：2001-12-18
申请号：US09684181
申请日：2000-10-07
Applicant: Zoran Cvetkovic , Ingrid Daubechies
Inventor： Zoran Cvetkovic , Ingrid Daubechies
IPC: H03M120
CPC classification number: H03M1/201
Abstract: A/D conversion is achieved by employing a piecewise continuous dither signal such that a signal that results from combining the dither signal with the signal to be converted, has a zero-crossing within each interval Ij=(jT,(j+1)T), where j is an integer, T=&pgr;/&lgr;B, B is the bandwidth of the signal to be converted, and &lgr; is a constant that is greater than 1, and those zero crossings in adjacent intervals Ij are always separated by some minimal distance, &egr;, for all intervals Ij. Zero crossings of the combined signal are detected, and the instances where those crossings occur are encoded; one zero crossing for each interval.
Abstract translation: 通过采用分段连续抖动信号来实现A / D转换，使得将抖动信号与要转换的信号组合的信号在每个间隔内具有零交叉Ij =（jT，（j + 1）T ），其中j是整数，T = pi / lambdB，B是要转换的信号的带宽，并且lambd是大于1的常数，并且相邻间隔Ij中的那些过零点总是被一些最小的 距离，epsi，对于所有间隔Ij。 检测到组合信号的零交叉，并且对这些交叉发生的情况进行编码; 每个间隔一个零交叉。
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公开(公告)号：US5497154A
公开(公告)日：1996-03-05
申请号：US296132
申请日：1994-08-26
Applicant: Mitsuya Komamura
Inventor： Mitsuya Komamura
CPC classification number: H03M1/0641 , H03M1/201 , H03M1/12
Abstract: A dither generating apparatus which generates a sufficiently random auto dither even for a small-level signal and even if the buffer length is short. The LSB of quantized data is extracted and is stored in a buffer memory which serves as an M-bit shift register. An index buffer storing old 2.sup.M indexes is referred to with the M bits. A look-up table, which outputs a random value, is referred to in accordance with the value in the index buffer and outputs a dither. After the reference to the look-up table, current M-bit data is input to the index buffer so that the content of the index buffer is shifted piece by piece. As the values of the outputs of the index buffer and the buffer memory are both always variable, different values are always supplied to the look-up table, which therefore generates sufficiently random dithers.
Abstract translation: 即使对于小电平信号也产生足够随机的自动抖动并且即使缓冲器长度短的抖动产生装置。 量化数据的LSB被提取并存储在用作M位移位寄存器的缓冲存储器中。 存储旧的2M索引的索引缓冲器被称为M位。 根据索引缓冲器中的值来引用输出随机值的查找表，并输出抖动。 在参考查找表之后，将当前的M位数据输入到索引缓冲器，使得索引缓冲器的内容逐个移位。 由于索引缓冲器和缓冲存储器的输出的值总是可变的，所以不断的值始终被提供给查找表，因此查找表产生足够的随机抖动。
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公开(公告)号：US5493298A
公开(公告)日：1996-02-20
申请号：US356923
申请日：1994-12-14
Applicant: Manfred U. Bartz
Inventor： Manfred U. Bartz
CPC classification number: H03M1/0641 , H03M1/201 , H03M1/12
Abstract: A dithered analog-to-digital converter includes a correlator to detect dither residue in the output signal. The correlator output is accumulated and used in a feedback loop to control the gain of the dither signal so as to null the residue. Problems associated with the low bandwidth of the feedback loop, and corruption of the accumulator value due to overload, are addressed by provision of a preload register from which the accumulator is initialized on power-up and on detection of an overload. This approach provides quick settling time and avoids statistical anomalies associated with decimation approaches to overload.
Abstract translation: 抖动模数转换器包括用于检测输出信号中的抖动残差的相关器。 相关器输出被积累并用在反馈环路中以控制抖动信号的增益，以使残余物无效。 通过提供预加载寄存器来解决与反馈环路的低带宽相关的问题以及由于过载而导致的累加器值的损坏，在预加载寄存器中，通过上电和检测到过载来初始化累加器。 这种方法提供了快速的建立时间，并避免了与抽取方法过载相关的统计异常。
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公开(公告)号：US5134399A
公开(公告)日：1992-07-28
申请号：US593441
申请日：1990-10-05
Applicant: Donald R. Hiller
Inventor： Donald R. Hiller
Abstract: Noise (dither) is introduced into a subranging analog-to-digital converter to enhance conversion accuracy. The resolution of the noise is sufficiently fine that its least significant bits can be changed without always changing the second pass approximation from the converter's internal analog-to-digital converter. Additional bits of statistical resolution can thereby be achieved without sacrificing the overlap between the dither word and the first pass digital approximation that is needed to provide dithered error correction.
Abstract translation: 将噪声（抖动）引入到子模块中，以提高转换精度。 噪声的分辨率足够精细，使得其最低有效位可以被改变而不必总是从转换器的内部模数转换器改变第二遍近似。 因此可以实现统计分辨率的附加位，而不会牺牲抖动字与提供抖动纠错所需的第一遍数字近似之间的重叠。
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