公开(公告)号：US10777528B2

公开(公告)日：2020-09-15

申请号：US15615693

申请日：2017-06-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

IPC: H01L21/56 ,  H01L21/786 ,  H01L21/784 ,  H01L23/00 ,  H01L23/31 ,  H01L21/782 ,  H01L21/82 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

公开(公告)号：US10658330B2

公开(公告)日：2020-05-19

申请号：US15626511

申请日：2017-06-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

公开(公告)号：US10515828B2

公开(公告)日：2019-12-24

申请号：US15274590

申请日：2016-09-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L21/56 ,  H01L23/28 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/3105

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

公开(公告)号：US10446523B2

公开(公告)日：2019-10-15

申请号：US15218847

申请日：2016-07-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Sheila Marie L. Alvarez ,  Yaojian Lin ,  Jose A. Caparas ,  Yang Kern Jonathan Tan

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L21/311 ,  H01L21/48 ,  H01L23/31 ,  H01L21/263

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

公开(公告)号：US10388612B2

公开(公告)日：2019-08-20

申请号：US15664734

申请日：2017-07-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

公开(公告)号：US20190109015A1

公开(公告)日：2019-04-11

申请号：US16206108

申请日：2018-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/13

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

公开(公告)号：US10204866B2

公开(公告)日：2019-02-12

申请号：US15381281

申请日：2016-12-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

公开(公告)号：US10163747B2

公开(公告)日：2018-12-25

申请号：US15461713

申请日：2017-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00

Abstract: A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.

公开(公告)号：US10163737B2

公开(公告)日：2018-12-25

申请号：US15169535

申请日：2016-05-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/498 ,  H01L21/66 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

公开(公告)号：US20180294236A1

公开(公告)日：2018-10-11

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.