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    REDUCED SIGNALING INTERFACE METHOD & APPARATUS
    103.
    发明申请
    REDUCED SIGNALING INTERFACE METHOD & APPARATUS 审中-公开

    公开(公告)号：US20160047860A1

    公开(公告)日：2016-02-18

    申请号：US14925536

    申请日：2015-10-28

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318558

    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

    Addressable tap selection aux i/o, linking, address, instruction, control circuitry
    104.
    发明授权
    Addressable tap selection aux i/o, linking, address, instruction, control circuitry 有权
    可寻址抽头选择辅助i / o，链接，地址，指令，控制电路

    公开(公告)号：US09217773B2

    公开(公告)日：2015-12-22

    申请号：US14567299

    申请日：2014-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318558

    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

    Abstract translation: 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。 在本公开的第五方面中，一种接口选择电路， 图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

    AT-SPEED TEST ACCESS PORT OPERATIONS
    105.
    发明申请
    AT-SPEED TEST ACCESS PORT OPERATIONS 审中-公开

    公开(公告)号：US20150355987A1

    公开(公告)日：2015-12-10

    申请号：US14830244

    申请日：2015-08-19

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G06F11/26

    CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/26 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L51/5212 ,  H01L51/5215 ,  H01L51/5253 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/301 ,  H01L2251/308

    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

    SCAN RESPONSE REUSE METHOD AND APPARATUS
    106.
    发明申请
    SCAN RESPONSE REUSE METHOD AND APPARATUS 审中-公开
    扫描响应重用方法和设备

    公开(公告)号：US20150338459A1

    公开(公告)日：2015-11-26

    申请号：US14735806

    申请日：2015-06-10

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

    Abstract translation: 本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并作为输入到被测电路的扫描输入的刺激数据的新的方法和装置。 此外，本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并用作预期数据以与从被测电路输出的响应数据进行比较的新颖方法和装置。 在本公开中还提供和描述了另外的实施例。

    TDO multiplexers series coupling augmentation instruction register with instruction registers
    110.
    发明授权
    TDO multiplexers series coupling augmentation instruction register with instruction registers 有权
    TDO多路复用器串联扩充指令寄存器与指令寄存器

    公开(公告)号：US09134376B2

    公开(公告)日：2015-09-15

    申请号：US14605329

    申请日：2015-01-26

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun ,  Lee D. Whetsel

    IPC: G01R31/28 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

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