公开(公告)号：US20170278947A1

公开(公告)日：2017-09-28

申请号：US15196024

申请日：2016-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed therebetween. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region. The present invention further provides a semiconductor fin structure.

公开(公告)号：US09735047B1

公开(公告)日：2017-08-15

申请号：US15172161

申请日：2016-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

公开(公告)号：US09711394B1

公开(公告)日：2017-07-18

申请号：US15161301

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/41791

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a substrate having an epitaxial layer, a gate structure and an interlayer dielectric thereon, where the epitaxial structure is disposed at sides of the gate structure and the interlayer dielectric covering the epitaxial structure; forming an opening in the interlayer dielectric so that the surface of the epitaxial layer is exposed from the bottom of the opening; performing a rapid thermal process in an inert environment until non-conductive material is generated on the surface of the epitaxial layer; and removing the non-conductive material.

公开(公告)号：US20170194203A1

公开(公告)日：2017-07-06

申请号：US15014034

申请日：2016-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/08

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US20170103981A1

公开(公告)日：2017-04-13

申请号：US14880284

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin

IPC: H01L27/07 ,  H01L29/06 ,  H01L21/283 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0629 ,  H01L28/00 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a patterned mask on the ILD layer; and using the patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

公开(公告)号：US09589966B2

公开(公告)日：2017-03-07

申请号：US14724775

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.

Abstract translation: 公开了一种静态随机存取存储器（SRAM）。 SRAM包括在衬底上的多个SRAM单元，其中每个SRAM单元包括：衬底上的栅极结构; 围绕栅极结构的第一层间电介质（ILD）层; 第一ILD层中的第一接触插塞; 第一ILD层上的第二ILD层; 以及在所述第二ILD层中的第二接触插塞，并且电连接到所述第一接触插塞。

公开(公告)号：US20160322366A1

公开(公告)日：2016-11-03

申请号：US14724775

申请日：2015-05-28

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.

Abstract translation: 公开了一种静态随机存取存储器（SRAM）。 SRAM包括在衬底上的多个SRAM单元，其中每个SRAM单元包括：衬底上的栅极结构; 围绕栅极结构的第一层间电介质（ILD）层; 第一ILD层中的第一接触插塞; 第一ILD层上的第二ILD层; 以及在所述第二ILD层中的第二接触插塞，并且电连接到所述第一接触插塞。

公开(公告)号：US20160247678A1

公开(公告)日：2016-08-25

申请号：US14629491

申请日：2015-02-24

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  An-Chi Liu ,  Chih-Wei Wu ,  Jyh-Shyang Jenq ,  Shih-Fang Hong ,  En-Chiuan Liou ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Mei-Chen Chen ,  Chia-Hsun Tseng

IPC: H01L21/033 ,  H01L21/66

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L22/12

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，提供具有多个心轴图案的图案化的硬掩模层。 接下来，通过图案化的硬掩模在基板上形成多个第一心轴。 接下来，执行至少一个侧壁图像传送（SIT）处理。 最后，在基板上形成多个散热片，其中每个翅片具有预定的临界尺寸（CD），并且每个心轴图案具有比预定CD大5-8倍的CD。

公开(公告)号：US09379119B1

公开(公告)日：2016-06-28

申请号：US14749623

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L23/48 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.

Abstract translation: 公开了一种静态随机存取存储器（SRAM）。 SRAM包括在衬底上的多个SRAM单元，其中每个SRAM单元还包括：衬底上的栅极结构，设置在衬底上的多个鳍结构，其中每个鳍结构垂直于排列方向排列 栅极结构周围的第一层间电介质（ILD）层，第一ILD层中的第一接触插塞，其中第一接触插塞为带状并接触两个不同的翅片结构; 和第一ILD层上的第二ILD层。

公开(公告)号：US09318334B2

公开(公告)日：2016-04-19

申请号：US14469606

申请日：2014-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Chih-Kai Hsu

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L27/092 ,  H01L21/308

CPC classification number: H01L21/28132 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有限定在其上的第一区域和第二区域的衬底; 在所述基板上形成多个鳍状结构; 在鳍状结构上形成栅极层; 在栅极层上形成材料层; 图案化用于在第一区域中的栅极层上形成牺牲心轴的材料层; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 在所述第二区域上形成图案化掩模; 并且利用图案化掩模和侧壁间隔物去除栅极层的一部分。