公开(公告)号：US20220261355A1

公开(公告)日：2022-08-18

申请号：US17177775

申请日：2021-02-17

Applicant: Microsoft Technology Licensing, LLC

Inventor： Thomas Philip SPEIER ,  Jason S. WOHLGEMUTH ,  Artur KLAUSER ,  Gagan GUPTA ,  Cody D. HARTWIG ,  Abolade GBADEGESIN

IPC: G06F12/1036 ,  G06F12/1045 ,  G06F12/0882 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F11/07

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address. In some embodiments, any address translation errors encountered are raised to an appropriate exception level, and may be raised synchronously or asynchronously with respect to an operation performed when the speculative translation instruction is executed.

公开(公告)号：US20220237039A1

公开(公告)日：2022-07-28

申请号：US17723846

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  H04L41/0896 ,  G06F12/02 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11314658B2

公开(公告)日：2022-04-26

申请号：US15574596

申请日：2016-04-28

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

IPC: G06F12/1036 ,  G06F12/02 ,  G06F12/14 ,  G06F12/10 ,  G06F9/455 ,  G06F12/1009

Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

公开(公告)号：US11287999B2

公开(公告)日：2022-03-29

申请号：US16897087

申请日：2020-06-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu ,  Zhou Yu

IPC: G06F12/1036 ,  G06F12/109 ,  G06F3/06 ,  G06F9/50 ,  G06Q10/10 ,  G06Q30/02

Abstract: A multi-instance 2-Level-Memory (2LM) architecture manages access by processing instances having different memory usage priorities to memory having different performance and cost levels. The 2LM architecture includes a virtual memory management module that manages access by respective processing instances by creating memory instances based on specified memory usage priority levels and specified virtual memory sizes and defining policies for each usage priority level of the created memory instances. In response to a virtual memory request by a processing instance, the virtual memory management module determines whether a virtual memory size at a designated usage priority level requested by a processing instance can be satisfied by a policy of a created first memory instance and, if not, selects another memory instance that can satisfy the requested virtual memory size at the designated usage priority level and swaps out the first memory instance in favor of the other memory instance.

公开(公告)号：US11243892B2

公开(公告)日：2022-02-08

申请号：US16745019

申请日：2020-01-16

Applicant: ARM Limited

Inventor： Steven Douglas Krueger

IPC: G06F12/1045 ,  G06F12/109 ,  G06F12/126 ,  G06F12/1027 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/1036 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/12

Abstract: A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

公开(公告)号：US20210374289A1

公开(公告)日：2021-12-02

申请号：US17393248

申请日：2021-08-03

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/74 ,  G06F21/72 ,  G06F9/30 ,  G06F12/1036 ,  G06F21/60

Abstract: Methods, systems, and apparatuses related to adjustable security levels in processors are described. A processor may have functional units and a register configured to control security operations of the functional units. The register configures the functional units to operate in a first mode of security operations when the register contains a first setting; and the register configures the functional units to operate in a second mode of security operations when the register contains a second setting (e.g., to skip/bypassing a set of security operation circuit for enhanced execution speed).

公开(公告)号：US11169745B1

公开(公告)日：2021-11-09

申请号：US16519832

申请日：2019-07-23

Applicant: PURE STORAGE, INC.

Inventor： Ethan Miller ,  John Colgrove ,  John Hayes

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1036

Abstract: An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.

公开(公告)号：US11102224B2

公开(公告)日：2021-08-24

申请号：US16553971

申请日：2019-08-28

Applicant: Palantir Technologies Inc.

Inventor： Alexander Visbal ,  James Thompson ,  Marvin Sum ,  Jason Ma ,  Bing Jie Fu ,  Ilya Nepomnyashchiy ,  Devin Witherspoon ,  Victoria Lai ,  Steven Berler ,  Alexei Smaliy ,  Suchan Lee

IPC: H04L29/06 ,  G06Q40/00 ,  G06F16/28 ,  G06F16/9038 ,  G06F16/2457 ,  G06F3/0482 ,  G06F3/0484 ,  G06Q40/02 ,  G06F12/1036 ,  G06K9/62 ,  G06F16/34 ,  G06F21/55

Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, automatically tag and group those clustered data structures, and provide results of the automated analysis and grouping in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a tiled display of the groups of related data clusters such that the analyst may quickly and efficiently evaluate the groups of data clusters. In particular, the groups of data clusters may be dynamically re-grouped and/or filtered in an interactive user interface so as to enable an analyst to quickly navigate among information associated with various groups of data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation.

公开(公告)号：US20210255962A1

公开(公告)日：2021-08-19

申请号：US17156175

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Krystof C. Zmudzinski ,  Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Ilya Alexandrovich ,  Ittai Anati ,  Wesley H. Smith ,  Michael Goldsmith

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14 ,  G06F9/455

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

公开(公告)号：US20210109684A1

公开(公告)日：2021-04-15

申请号：US17131731

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： VEDVYAS SHANBHOGUE ,  JASON W. BRANDT ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY ,  BAIJU V. PATEL

IPC: G06F3/06 ,  G06F9/30 ,  G06F21/52 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1036

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.