-
公开(公告)号：US20120204013A1
公开(公告)日：2012-08-09
申请号：US13310508
申请日：2011-12-02
Applicant: Craig HANSEN , John MOUSSOURIS , Alexia MASSALIN
Inventor： Craig HANSEN , John MOUSSOURIS , Alexia MASSALIN
IPC: G06F9/302
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
Abstract translation: 提出了一种可编程处理器的系统和装置，其包括执行单元，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行群组数据处理 响应于数据处理指令以不同方式重新布置数据元素的操作，所述执行单元还能够执行多个不同的组浮点和组整数运算，每个算术运算对存储在寄存器中的多个数据元素进行算术运算 该寄存器文件产生一个返回到该寄存器文件中的一个寄存器的连线结果，其中该连接结果包括多个单独的结果。
-
112.发明授权System and method to implement a matrix multiply unit of a broadband processor 失效实现宽带处理器的矩阵乘法单元的系统和方法公开(公告)号：US08195735B2
公开(公告)日：2012-06-05
申请号：US12330962
申请日：2008-12-09
Applicant: Craig Hansen , Bruce Bateman , John Moussouris
Inventor： Craig Hansen , Bruce Bateman , John Moussouris
CPC classification number: G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。
-
公开(公告)号：US08001360B2
公开(公告)日：2011-08-16
申请号：US10757925
申请日：2004-01-16
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
Abstract translation: 一种用于通过结合执行单元来提高处理器的性能的系统和软件，所述执行单元可操作以解码和执行指定数据选择操作数的单个指令，以及提供多个数据元素的第一和第二寄存器，所述数据选择操作数包括多个字段 每个选择所述多个数据元素中的一个，所述执行单元可操作以将所述数据选择操作数的每个字段所选择的数据元素提供到预定位置。
-
114.发明授权公开(公告)号：US07932910B2
公开(公告)日：2011-04-26
申请号：US11894584
申请日：2007-08-20
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
-
公开(公告)号：US07818548B2
公开(公告)日：2010-10-19
申请号：US11878804
申请日：2007-07-27
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/315
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions, (b) in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, and (c) in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways.
Abstract translation: 提出了用于处理可编程处理器中的数据的方法和软件，其涉及（a）使用执行单元来解码执行指令，所述执行单元可操作以通过将存储在寄存器文件中的寄存器中的数据分割成多个数据元素来执行指令，所述指令从指令中选择 设置为包括组算术指令和组数据处理指令，（b）响应于解码不同组算术指令，执行对存储在寄存器中的多个数据元素进行算术运算的多个不同的组浮点和组整数运算 所述寄存器文件产生返回到所述寄存器文件中的寄存器的接合结果，其中所述接合结果包括多个单独的结果，以及（c）响应于解码不同的组数据处理指令，执行组数据处理操作， 以不同的方式重新排列数据元素。
-
Patent Agency Ranking
公开(公告)号：US07730287B2
公开(公告)日：2010-06-01
申请号：US11878814
申请日：2007-07-27
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions, (b) in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways, and (c) in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
Abstract translation: 提出了用于处理可编程处理器中的数据的方法和软件，其涉及（a）使用执行单元来解码执行指令，所述执行单元可操作以通过将存储在寄存器文件中的寄存器中的数据分割成多个数据元素来执行指令，所述指令从指令中选择 设置为包括组算术指令和组数据处理指令，（b）响应于解码不同组数据处理指令，执行以不同方式重新排列数据元素的组数据处理操作，以及（c）响应于解码不同组 算术指令，执行对存储在寄存器文件中的寄存器中的多个数据元素进行算术运算的多个不同的组浮点和组整数算术运算，以产生返回到寄存器堆中的寄存器的联结结果，其中 连带结果包括多个单独的结果 lts。
-
公开(公告)号：US20090158012A1
公开(公告)日：2009-06-18
申请号：US11842038
申请日：2007-10-29
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
Abstract translation: 提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个 不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果 其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。
-
118.发明申请SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 失效用于实现宽带处理器的矩阵多项式单元的系统和方法公开(公告)号：US20090094309A1
公开(公告)日：2009-04-09
申请号：US12330962
申请日：2008-12-09
Applicant: Craig HANSEN , Bruce Bateman , John Moussouris
Inventor： Craig HANSEN , Bruce Bateman , John Moussouris
CPC classification number: G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。
-
公开(公告)号：US07216217B2
公开(公告)日：2007-05-08
申请号：US10646787
申请日：2003-08-25
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/30167 , G06F9/383 , G06F9/3834 , G06F12/0875
Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.
Abstract translation: 一种可编程处理器，其包括能够独立于另一主机处理器的操作的通用处理器架构，具有虚拟存储器寻址单元，指令路径和数据路径; 外部接口; 缓存，用于保持在所述外部接口和所述数据路径之间传送的数据; 至少一个寄存器文件，其被配置为从所述数据路径接收和存储数据并将所存储的数据传送到所述数据路径; 以及耦合到数据路径的多精度执行单元。 多精度执行单元可配置为动态分割从数据路径接收到的数据，以考虑数据的基本宽度，并且能够对操作数寄存器的分区字段中的多个操作数执行组浮点运算，并返回联结结果。 在其他实施例中，多精度执行单元另外可配置为执行组整数和/或组数据处理操作。
-
120.发明申请公开(公告)号：US20040215942A1
公开(公告)日：2004-10-28
申请号：US10757515
申请日：2004-01-15
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/00
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A system and software for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.
Abstract translation: 一种用于通过结合执行单元来配置以执行来自多个线程的多个指令流的执行单元来提高处理器的性能的系统和软件，其中每个指令流包括对分组字段中的多个数据元素进行操作的组指令 至少有一个寄存器产生连带结果。
-
-
-
-
-
-
-
-
-
Search Results
137
records
(took 0.077 seconds)
