APPARATUS AND METHODS TO RENDER 3D DIGITAL CONTENT HAVING MULTIPLE VIEWS

    公开(公告)号:US20250044609A1

    公开(公告)日:2025-02-06

    申请号:US18920130

    申请日:2024-10-18

    Abstract: An example device includes a screen, a first light source configured to emit a first light at a first angle during a first time period and a second light source configured to emit a second light at a second angle during a second time period. The second angle is different than the first angle. The second time period is different than the first time period. The device includes a spatial light modulator configured to provide a first view of digital content based on the first angle of the first light emitted during the first time period and a second view of the digital content based on the second angle of the second light emitted during the second time period and projection optics configured to project the first view and the second view for presentation via the screen.

    BLE channel aware operation parameters

    公开(公告)号:US12219450B2

    公开(公告)日:2025-02-04

    申请号:US17850784

    申请日:2022-06-27

    Abstract: In an example, a method includes communicating between a first BLUETOOTH device and a second BLUETOOTH device via a first channel within a channel set at a first connection event using first channel specific parameters. The method also includes determining, by the first BLUETOOTH device, one or more channel cluster operation parameters for a second channel within the channel set at a second connection event using second channel specific parameters. The method includes communicating over the second channel during the second connection event from the first BLUETOOTH device to the second BLUETOOTH device using renegotiated second channel specific parameters.

    False collectors and guard rings for semiconductor devices

    公开(公告)号:US12218190B2

    公开(公告)日:2025-02-04

    申请号:US17731510

    申请日:2022-04-28

    Abstract: A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

    ELECTRONIC DEVICE WITH LEAD LOCK
    118.
    发明申请

    公开(公告)号:US20250038077A1

    公开(公告)日:2025-01-30

    申请号:US18360873

    申请日:2023-07-28

    Abstract: An electronic device includes a leadframe having a die pad, inner leads, and outer leads. The die is attached to the die pad, where the die includes an active side. Lead locks are disposed adjacent to the inner leads. The lead locks include a side support disposed on each side of the inner leads and an opening defined between each side support and the inner leads. Wire bonds are attached from the active side of the die to the inner leads and a mold compound is formed to encapsulate the die, the inner leads, the lead locks, and the wire bonds.

    STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE

    公开(公告)号:US20250038009A1

    公开(公告)日:2025-01-30

    申请号:US18361747

    申请日:2023-07-28

    Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.

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