公开(公告)号：US20040186950A1

公开(公告)日：2004-09-23

申请号：US10816076

申请日：2004-03-31

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G06F012/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US20040139296A1

公开(公告)日：2004-07-15

申请号：US10743468

申请日：2003-12-23

Applicant: Intel Corporation

Inventor： Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrat

IPC: G06F015/00 ,  G06F015/76 ,  G06F013/28

CPC classification number: G06F12/0813 ,  G06F15/8015 ,  G11C7/1036

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract translation: 在单个集成电路上作为外部主器件的从器件的存储器组件包括RAM，一个或多个配置寄存器，数据格式化逻辑和相关联的控制逻辑。 存储器组件的行为，特别是突发传输格式的选择，可以通过一个或多个配置寄存器中的配置寄存器位进行控制。 具体地，基于由配置位指定的格式选择，控制逻辑确定RAM和外部主设备之间的数据传输的序列长度。 除了序列长度之外，在数据传输期间数据不会另外更改。

公开(公告)号：US20040085848A1

公开(公告)日：2004-05-06

申请号：US10688881

申请日：2003-10-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C008/02

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.

Abstract translation: 一种访问与时钟信号同步操作的半导体器件的方法，包括：与时钟信号同步地取得表示存储单元阵列中的存储单元位置的信息，确定顺序传送的多个数据的第一数据，解码 指示存储单元阵列中的存储单元位置的信息并指定存储单元，在预定数量的存储单元阵列之后，与指示存储单元阵列中的存储单元位置的信息同步地接收存储在存储单元阵列中的信息，与时钟信号同步地接收存储单元 时钟信号的周期，并且与时钟信号同步地输出存储在存储单元中的多个数据，并与时钟信号同步地将多个输入数据存储在存储单元中。

公开(公告)号：US06728829B2

公开(公告)日：2004-04-27

申请号：US10448934

申请日：2003-05-30

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

公开(公告)号：US06727876B2

公开(公告)日：2004-04-27

申请号：US09956746

申请日：2001-09-18

Applicant: Chang-sig Kang

Inventor： Chang-sig Kang

IPC: G09G336

CPC classification number: G11C8/04 ,  G09G3/3688 ,  G11C7/1036

Abstract: A thin film transistor (TFT) liquid crystal device (LCD) driver capable of reducing current consumption is provided. The TFT LCD driver includes a gate driver for driving gate lines of a panel formed of a plurality of transistors and capacitors, and a source driver for driving source lines of the panel. The source driver includes a shift register portion, a latch clock signal generating portion, and a data latching portion. The shift register portion includes first through n-th flip-flops, into which a multiplied signal of an external clock signal is input as a clock signal, and input and output terminals of the flip-flops are connected in series, and provides a driving pulse signal as an input signal of the first flip-flop in response to the clock signal. The latch clock signal generating portion generates first through n-th latch clock signals by logically multiplying first through n-th middle driving pulse signals generated by the corresponding first through n-th flip-flops by inverted signals of first through n-th output signals. The data latching portion receives data signals and includes first through n-th latches for latching and outputting the data signals in response to the corresponding first through n-th latch clock signals. Current consumed by the driver is reduced by the TFT LCD driver.

Abstract translation: 提供了能够降低电流消耗的薄膜晶体管（TFT）液晶装置（LCD）驱动器。 TFT LCD驱动器包括用于驱动由多个晶体管和电容器形成的面板的栅极线的栅极驱动器和用于驱动面板的源极线的源极驱动器。 源极驱动器包括移位寄存器部分，锁存时钟信号产生部分和数据锁存部分。 移位寄存器部分包括第一至第n触发器，其中输入外部时钟信号的相乘信号作为时钟信号，并且触发器的输入和输出端串联连接，并提供驱动 脉冲信号作为响应于时钟信号的第一触发器的输入信号。 锁存时钟信号产生部分通过逻辑乘法由第一至第n触发器产生的第n到第n个中间驱动脉冲信号，通过第一至第n输出信号的反相信号产生第一到第n个锁存时钟信号 。 数据锁存部分接收数据信号，并包括第一至第n锁存器，用于响应于对应的第一至第n锁存时钟信号而锁存和输出数据信号。 驱动器消耗的电流由TFT LCD驱动器减少。

公开(公告)号：US06654314B2

公开(公告)日：2003-11-25

申请号：US10359190

申请日：2003-02-06

Applicant: Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C700

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.

Abstract translation: 一种访问与时钟信号同步操作的半导体器件的方法，包括：与时钟信号同步地取得表示存储单元阵列中的存储单元位置的信息，确定顺序传送的多个数据的第一数据，解码 指示存储单元阵列中的存储单元位置的信息并指定存储单元，在预定数量的存储单元阵列之后，与指示存储单元阵列中的存储单元位置的信息同步地接收存储在存储单元阵列中的信息，与时钟信号同步地接收存储单元 时钟信号的周期，并且与时钟信号同步地输出存储在存储单元中的多个数据，并与时钟信号同步地将多个输入数据存储在存储单元中。

公开(公告)号：US06587374B2

公开(公告)日：2003-07-01

申请号：US10082045

申请日：2002-02-20

Applicant: Hiroki Takagi ,  Yoshihiro Tada ,  Noriaki Katsuhara

Inventor： Hiroki Takagi ,  Yoshihiro Tada ,  Noriaki Katsuhara

IPC: G11C1604

CPC classification number: G11C16/10 ,  G11C7/1036 ,  G11C16/26 ,  G11C2216/30

Abstract: Memory cells of a storage device are addressed in n-bit word(s). Each of the n-bit word memory cells are partitioned into k (k≧2) groups of n/k bits. The memory cells are sequentially selected in n/k bits. Data of the selected n/k bit memory cells are read by n/k sense amplifiers and serially output from the storage device as readout data. The storage device requires much less chip area for n/k sense amplifiers and reduced peak currents in a read operation.

公开(公告)号：US06560146B2

公开(公告)日：2003-05-06

申请号：US09956416

申请日：2001-09-17

Applicant: Raul Adrian Cernea

Inventor： Raul Adrian Cernea

IPC: G11C700

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

公开(公告)号：US20030084267A1

公开(公告)日：2003-05-01

申请号：US10284774

申请日：2002-10-31

Inventor： Maksim Kuzmenka

IPC: G06F009/26

CPC classification number: G11C8/04 ,  G11C7/1036

Abstract: A device is provided for accessing circuit units via access registers. The circuit units have a plurality of inputs for access to said circuit units. A first access register having register outputs which are connected to a first part of the inputs of at least one first circuit unit, and having register outputs which are connected to inputs of at least one second circuit unit is provided. In addition, a second access register having register outputs which are connected to a second part of the inputs of said at least one first circuit unit, and having register outputs connected to inputs of at least one third circuit unit is provided. Moreover, an access register is provided which has a number of register inputs, first register outputs for driving the inputs of at least one first circuit unit, each register input having associated therewith a first register output, and second register outputs for driving part of the inputs of at least one second circuit unit, a subset of the register inputs having associated therewith a second register output.

Abstract translation: 提供了一种通过访问寄存器访问电路单元的设备。 电路单元具有用于访问所述电路单元的多个输入。 提供具有连接到至少一个第一电路单元的输入的第一部分并且具有连接到至少一个第二电路单元的输入的寄存器输出的寄存器输出的第一访问寄存器。 此外，提供了具有连接到所述至少一个第一电路单元的输入的第二部分并且具有连接到至少一个第三电路单元的输入的寄存器输出的寄存器输出的第二访问寄存器。 此外，提供了一种访问寄存器，其具有多个寄存器输入，第一寄存器输出用于驱动至少一个第一电路单元的输入，每个寄存器输入具有与其相关联的第一寄存器输出，以及第二寄存器输出，用于驱动部分 至少一个第二电路单元的输入，与其相关联的寄存器输入的子集第二寄存器输出。

公开(公告)号：US06535456B2

公开(公告)日：2003-03-18

申请号：US10093935

申请日：2002-03-11

Applicant: Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C800

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor device includes a memory cell array, a counting section, a control section, a specification section and a data input/output section. The counting section configured to count transition of the clock signal and determine first data of a plurality of data to be transferred sequentially. The control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of the counting section and control consecutive input and output of a plurality of data stored in the memory cell array every cycle of the clock signal. The specification section configured to decode the information fetched by the control section and designate a memory cell in the memory cell array. The data input/output section configured to input data to or output data from the memory cell designated by the specification section, wherein input and output of the data are time-shared.

Abstract translation: 半导体器件包括存储单元阵列，计数部，控制部，指定部和数据输入输出部。 所述计数部分被配置为对所述时钟信号的转换进行计数，并且确定顺序地传送的多个数据的第一数据。 所述控制部分被配置为响应于所述计数部分的计数结果来提取指示所述存储单元阵列中的存储器单元位置的信息，并且每周期的所述时钟信号控制存储在所述存储单元阵列中的多个数据的连续输入和输出 。 所述规格部分被配置为对由所述控制部分获取的信息进行解码并指定所述存储器单元阵列中的存储器单元。 数据输入/输出部分被配置为向由指定部分指定的存储单元输入数据或从其输出数据，其中数据的输入和输出是时间共享的。