公开(公告)号：US20150325552A1

公开(公告)日：2015-11-12

申请号：US14706896

申请日：2015-05-07

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/12105 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48464 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2924/00

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一器件衬底的芯片封装。 第一器件衬底附接到第二器件衬底的第一表面。 第三器件衬底附接到与第一表面相对的第二器件衬底的第二表面。 绝缘层覆盖第一，第二和第三器件衬底，并且在其中具有至少一个开口。 至少一个凸起设置在开口的底部下方。 再分配层设置在绝缘层上并通过开口与凸块电连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20150318348A1

公开(公告)日：2015-11-05

申请号：US14699261

申请日：2015-04-29

Applicant: XINTEC INC.

Inventor： Yu-Lin YEN ,  Sheng-Hao CHIANG ,  Hung-Chang CHEN ,  Ho-Ku LAN ,  Chen-Mei FAN

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0642 ,  H01L21/76229 ,  H01L27/1463 ,  H01L27/14683

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract translation: 半导体结构包括基板，阻挡元件，第一隔离层，第二隔离层和导电层。 衬底具有导电焊盘，沟槽，侧壁，第一表面和与第一表面相对的第二表面。 导电垫位于第二表面上。 沟槽在第一表面具有第一开口，并且在第二表面具有第二开口。 坝体元件位于第二表面并覆盖第二开口。 坝体元件具有在第二开口处的凹入部分。 第一隔离层位于侧壁的一部分上。 第二隔离层位于不被第一隔离层覆盖的第一表面和侧壁上，使得在第一和第二隔离层之间形成界面。

公开(公告)号：US20150099357A1

公开(公告)日：2015-04-09

申请号：US14508989

申请日：2014-10-07

Applicant: XINTEC INC.

Inventor： Chuan-Jin SHIU ,  Tsang-Yu LIU ,  Chih-Wei HO ,  Shih-Hsing CHAN ,  Ching-Jui CHUANG

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/32139 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/11821 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/0105 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Abstract translation: 提供了制造晶片级芯片封装的方法。 首先，提供具有两个相邻芯片的晶片，所述晶片具有上表面和下表面，并且每个芯片的一侧在下表面上包括导电焊盘。 凹部和隔离层从上表面延伸到下表面，凹部暴露导电垫。 隔离层的一部分设置在具有开口的凹部中以暴露导电垫。 在隔离层和导电焊盘上形成导电层，并且将光致抗蚀剂层喷涂在导电层上。 曝光和显影光致抗蚀剂层以暴露导电层，并且蚀刻导电层以形成再分布层。 在剥离光刻胶层之后，在隔离层和再分布层上形成焊料层。

公开(公告)号：US08993365B2

公开(公告)日：2015-03-31

申请号：US14191348

申请日：2014-02-26

Applicant: Xintec Inc.

Inventor： Yi-Ming Chang ,  Kuo-Hua Liu ,  Yi-Cheng Wang ,  Sheng-Yen Chang

IPC: H01L21/00 ,  H01L31/0203 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract translation: 晶片封装方法包括以下步骤。 提供具有多个集成电路单元的晶片。 与集成电路单元相对的晶片的第一表面被研磨。 剥离层形成在透光载体的第二表面上。 在透光载体的第二表面或晶片的第三表面上形成紫外线临时粘接层。 紫外线暂时接合层用于将透光载体的第二表面粘附到晶片的第三表面。 晶片的第一表面粘附到紫外线带上。 透光载体的第四表面暴露于紫外线以消除紫外线临时粘合层的粘附力。 去除透光载体和释放层。

公开(公告)号：US08975739B2

公开(公告)日：2015-03-10

申请号：US14152970

申请日：2014-01-10

Applicant: Xintec Inc.

Inventor： Ming-Chung Chung

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/76885 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括衬底，电子芯片，焊盘，第一钝化层，导电层，第二钝化层和焊球。 导电层具有第一侧端和第二侧端，并且焊球位于导电层的第一侧端。 第二钝化层与导电层的第二侧端的上表面和侧壁接触，并且第一钝化层与导电层的第二侧端的下表面接触，以便完全封装第二钝化层 导电层的端部。 因此，电子装置封装防止了水分渗透并提高了电子设备的可靠性。

公开(公告)号：US08963312B2

公开(公告)日：2015-02-24

申请号：US14339341

申请日：2014-07-23

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US08952501B2

公开(公告)日：2015-02-10

申请号：US13950101

申请日：2013-07-24

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的半导体衬底; 限定在所述半导体衬底中的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 至少两个从所述半导体衬底的上表面向下表面延伸的凹槽，其中所述凹槽的侧壁和底部一起形成所述半导体衬底的侧壁; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US08928098B2

公开(公告)日：2015-01-06

申请号：US13714218

申请日：2012-12-13

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

公开(公告)号：US20140332985A1

公开(公告)日：2014-11-13

申请号：US14341573

申请日：2014-07-25

Applicant: XINTEC INC.

Inventor： Ching-Yu NI ,  Chia-Ming CHENG ,  Nan-Chun LIN

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。 多个导电焊盘设置在外围接合焊盘区域处，并且钝化层形成在半导体衬底上以露出导电焊盘。 在器件区域的钝化层上形成绝缘保护层。 封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。 该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘，并且通过封装层的开口去除导电焊盘上的绝缘保护层。

公开(公告)号：US20140332969A1

公开(公告)日：2014-11-13

申请号：US14339355

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN ,  Chi-Chang LIAO

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3701 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的芯片的芯片封装。 芯片包括与上表面相邻的信号焊盘区域。 第一凹部沿着侧壁从上表面向下表面延伸。 至少一个第二凹部从第一凹部的第一底部向下表面延伸。 第一和第二凹部沿着上表面的侧面进一步横向延伸，并且沿着侧面延伸的第一凹部的长度大于沿着侧面延伸的第二凹部的长度。 再分配层电连接到信号焊盘区域并延伸到第二凹槽中。 还提供了一种用于形成芯片封装的方法。