公开(公告)号：US06720649B2

公开(公告)日：2004-04-13

申请号：US10211430

申请日：2002-08-02

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2310

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge corners of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.

公开(公告)号：US06703691B2

公开(公告)日：2004-03-09

申请号：US09991305

申请日：2001-11-14

Applicant: Nan-Jang Chen ,  Kevin Chiang ,  Chien-Ping Huang ,  Tzong-Da Ho

Inventor： Nan-Jang Chen ,  Kevin Chiang ,  Chien-Ping Huang ,  Tzong-Da Ho

IPC: H01L23495

CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract translation: 提出了一种QFN（四方扁平无铅）半导体封装技术，其可用于封装中心焊盘型半导体芯片，该半导体芯片具有沿着半导体芯片的一个表面上的中心线布置的至少一行接合焊盘 。 所提出的半导体封装技术基于特殊设计的引线框架，该引线框架形成有多个引线，芯片支撑和接地结构以及至少一个地面翼; 其中芯片支撑和接地结构既用作封装芯片的管芯焊盘和接地总线，并且接地翼与芯片支撑和接地结构电连接。 封装工艺完成后，地面翼和外引线部分暴露在封装体外侧的底部，然后在SMT（表面贴装技术）工艺中将PCB的接地平面接合，从而提高接地效果 以及操作期间封装芯片的电气性能。

公开(公告)号：US06661089B2

公开(公告)日：2003-12-09

申请号：US10137834

申请日：2002-05-03

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2348

CPC classification number: H01L21/6835 ,  H01L23/057 ,  H01L23/3157 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Disclosed is a semiconductor package which has no resinous flash formed on a lead frame and its manufacturing method. The method includes the steps of preparing a lead frame having a first surface and a second surface, attaching an adhesive tape capable of being easily removed on the second surface of the lead frame, attaching a first semiconductor chip on the lead frame and electrically connecting the first semiconductor chip with the lead frame, performing a molding process to form a resin molded block on the first surface of the lead frame for covering the first semiconductor chip, removing the adhesive tape, attaching a second semiconductor chip on the second surface and electrically connecting the second semiconductor chip with the lead frame, attaching a frame with a hollow portion on a predetermined position of the second surface of the lead frame by an adhesive agent and containing the second semiconductor chip in the hollow portion, and bonding a covering member on the frame to seal the hollow portion for isolating the second semiconductor chip from outside.

Abstract translation: 公开了一种在引线框上形成树脂闪光的半导体封装及其制造方法。 该方法包括以下步骤：制备具有第一表面和第二表面的引线框架，将能够容易地移除到引线框架的第二表面上的粘合带，将第一半导体芯片附接到引线框架上，并将 具有引线框架的第一半导体芯片，在引线框架的第一表面上进行成型工艺以形成树脂模制块，以覆盖第一半导体芯片，去除粘合带，将第二半导体芯片附接在第二表面上并电连接 具有引线框架的第二半导体芯片，通过粘合剂将具有中空部分的框架附接到引线框架的第二表面的预定位置，并且在中空部分中容纳第二半导体芯片，并且将覆盖构件 框架以密封用于将第二半导体芯片与外部隔离的中空部分。

公开(公告)号：US06593658B2

公开(公告)日：2003-07-15

申请号：US10001862

申请日：2001-11-19

Applicant: Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

Inventor： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

IPC: H01L2348

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

公开(公告)号：US06545332B2

公开(公告)日：2003-04-08

申请号：US10037895

申请日：2001-10-22

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L310203

CPC classification number: H01L27/14618 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary of the leads and located on a first surface of the lead frame. A plurality of bonding pads is formed on the active surface of a chip. A plurality of wires is utilized to electrically connect the bonding pads respectively to bonding portions of the leads on a first surface of the lead frame. A liquid compound is filled in between the chip and the molding structure and covering portions of the leads, A transmittance lid is allocated over the active surface, sealing the space between the molding structure and the lead frame.

公开(公告)号：US06538321B2

公开(公告)日：2003-03-25

申请号：US09946999

申请日：2001-09-05

Applicant: Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC: H01L2310

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

公开(公告)号：US06483039B2

公开(公告)日：2002-11-19

申请号：US09946902

申请日：2001-09-05

Applicant: Chien-Ping Huang ,  Tzong-Da Ho ,  Chen-Hsu Hsiao

Inventor： Chien-Ping Huang ,  Tzong-Da Ho ,  Chen-Hsu Hsiao

IPC: H05K103

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/284 ,  H05K3/3452 ,  H05K2201/09781 ,  H05K2201/099 ,  Y10S438/976 ,  Y10T29/49174 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A substrate of a semiconductor package is proposed, which is formed with a strip copper layer on a core layer of the substrate, wherein a solder mask is arranged to cover the core layer and two lengthwise sides of the copper layer by a width between 0.1 mm to 1.0 mm, while a surface between the sides of the copper layer is exposed by forming a groove opening to the atmosphere and plated with gold. This makes bulges generated by shrinkage of the solder mask covering the sides of the copper layer extend outwardly in a direction away from the groove opening, allowing clamping force to be sufficiently exerted on the substrate by a mold during an encapsulation process. As such, after completing the encapsulation process, an encapsulating resin remained in the runner can be easily removed without damaging the substrate, and also resin flash can be prevented from occurrence.

公开(公告)号：US06414384B1

公开(公告)日：2002-07-02

申请号：US09746793

申请日：2000-12-22

Applicant: Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

Inventor： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

IPC: H01L2302

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure stacking chips on a front surface and a back surface of a substrate including at least a substrate, a plurality of chip sets, a plurality of support members, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. Each chip set has one or more chips, each chip having a plurality of bonding pads. The chip sets are stacked as a laminate on the front surface of the substrate, respectively. A plurality of support members are arranged between each two adjacent chip sets. A glue layers are used to connect the support members, the chip sets, and the substrate. The chip in the same chip sets is electrically connected to each other or to the substrate by the bonding pads. Finally, the front surface of the substrate, the support members, the chip sets, and the glue layers are encapsulated with a mold compound. Moreover, a plurality of flip chips are deposited on the back surface of the substrate.

Abstract translation: 一种封装结构，其在至少包括基板，多个芯片组，多个支撑部件，多个胶合层，多个导线和模具化合物的基板的前表面和背面上堆叠芯片。 基板具有与前表面相对的前表面和后表面。 每个芯片组具有一个或多个芯片，每个芯片具有多个焊盘。 芯片组分别作为层叠体堆叠在基板的前表面上。 在每个两个相邻的芯片组之间布置有多个支撑构件。 使用胶层来连接支撑部件，芯片组和基板。 相同芯片组中的芯片通过焊盘彼此电连接或与基板电连接。 最后，用模具化合物包封衬底的前表面，支撑构件，芯片组和胶层。 此外，在基板的背面上沉积多个倒装芯片。

公开(公告)号：US06353257B1

公开(公告)日：2002-03-05

申请号：US09574598

申请日：2000-05-19

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2312

CPC classification number: H01L23/49548 ,  H01L23/057 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14618 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16195 ,  H01L2224/05599

Abstract: A semiconductor package configuration is proposed for use to pack an semiconductor chip of an optically-sensitive type, such as an image-sensor chip or an ultraviolet-sensitive EP-ROM chip. This type of semiconductor chips are encapsulated in an encapsulation body having a centrally-hollowed portion whose opening is covered with a lid. This semiconductor package configuration is characterized in the use of a lead frame having a die-pad portion formed with a shouldered portion at the edge thereof and having a lead portion formed with a recessed portion at the point where the inner wall of the centrally-hollowed portion of the encapsulation body is located. The shoulder portion and the recessed portion are used to help prevent the flash of resin on lead frame during the molding process to form the encapsulation body in the manufacture of the semiconductor package configuration. As a result, it can help assure the quality of the bonding of the semiconductor chip on the die-bonding area of the die pad as well as the bonding of gold wires to the wire-bonding area on the leads of the lead frame.

Abstract translation: 提出了一种用于封装诸如图像传感器芯片或紫外线敏感的EP-ROM芯片的光敏型半导体芯片的半导体封装结构。 这种类型的半导体芯片被封装在具有中空中空部分的封装体中，该中心部分的开口被盖子覆盖。 该半导体封装结构的特征在于使用具有在其边缘处形成有肩部的芯片焊盘部分的引线框架，并且具有在中心中空的内壁处形成有凹部的引线部分 位于封装体的一部分。 肩部和凹部用于在模制过程中防止引线框架上的树脂闪光，以在半导体封装结构的制造中形成封装体。 结果，这可以有助于确保半导体芯片在芯片焊盘的芯片接合区域上的接合质量以及金线与引线框架的引线上的引线接合区域的接合。

公开(公告)号：US08564115B2

公开(公告)日：2013-10-22

申请号：US13492220

申请日：2012-06-08

Applicant: Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

Inventor： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC: H01L23/04

CPC classification number: H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

Abstract translation: 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。