公开(公告)号：US09973754B2

公开(公告)日：2018-05-15

申请号：US14661711

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Pavan Venkata Shastry

IPC: H04N19/115 ,  H04N19/423 ,  G06F13/28

CPC classification number: H04N19/115 ,  G06F13/28 ,  H04N19/423

Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.

公开(公告)号：US09854252B2

公开(公告)日：2017-12-26

申请号：US14282211

申请日：2014-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/17 ,  H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20170132754A1

公开(公告)日：2017-05-11

申请号：US15143491

申请日：2016-04-29

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06T3/40 ,  G06T1/60 ,  G06T1/20

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US09473784B2

公开(公告)日：2016-10-18

申请号：US14279318

申请日：2014-05-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/89 ,  H04N19/14 ,  H04N19/82 ,  H04N19/436 ,  H04N19/176 ,  H04N19/117 ,  H04N19/186 ,  H04N19/182 ,  H04N19/423 ,  H04N19/102

CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/423 ,  H04N19/82

Abstract: A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel.

Abstract translation: 提供了一种用于在SAO组件中的视频帧的最大编码单元（LCU）的采样自适应偏移（SAO）滤波的方法，其包括由SAO组件接收到LCU的解块像素块可用的指示，以及应用 通过SAO分量对SAO处理区域的对应于该LCU的SAO处理区域的每个像素块进行SAO滤波，其中SAO处理区域的每个像素块的像素被并行地滤波。

公开(公告)号：US09372817B2

公开(公告)日：2016-06-21

申请号：US14330553

申请日：2014-07-14

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan

IPC: H04N19/433 ,  G06F13/28

CPC classification number: G06F13/28

Abstract: This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and reduces CPU intervention using virtual alignment, sub-tile optimization, transaction breakdown strategy, 4D indexing, a dedicated interface with the host and frame padding. The VDMA has separate buffers for non-determinative synchronous data transfers and determinative asynchronous data transfers.

Abstract translation: 用于VDMA的本发明将实现每秒30帧的超高分辨率（4K）编码/解码。 本发明使互连/ DDR利用率最大化，并使用虚拟对准，子块优化，事务分解策略，4D索引，与主机和帧填充的专用接口来减少CPU干预。 VDMA具有用于非确定性同步数据传输和确定性异步数据传输的单独缓冲器。

公开(公告)号：US20140341271A1

公开(公告)日：2014-11-20

申请号：US14282211

申请日：2014-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/50 ,  H04N19/13 ,  H04N19/107 ,  H04N19/119 ,  H04N19/124 ,  H04N19/60

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

Abstract translation: 提供了一种解封处理视频的过滤方法。 经处理的视频包括多个块，并且每个块包括多个子块。 多个块中的当前块包括垂直边缘和水平边缘。 经处理的视频还包括一组对应于当前块的控制参数和重构像素。 在当前块的垂直边缘和水平边缘估计边界强度指数。 加载控制参数集合，对应于当前块的重构像素和对应于一组相邻子块的部分滤波像素。 基于边界强度指数和控制参数集合对当前块的垂直边缘和水平边缘进行滤波，使得在对当前块的至少一个水平边缘进行滤波之前对当前块的垂直边缘进行滤波。

公开(公告)号：US20250156354A1

公开(公告)日：2025-05-15

申请号：US18933348

申请日：2024-10-31

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Arumbuliyur Govindarajan ,  Sai Karthik Rajaraman ,  Pratheesh Gangadhar Thalakkal Kottila Veedu ,  Niraj Nandan ,  Mel Alan Phipps

IPC: G06F13/28

Abstract: An example accelerator circuit includes a direct memory access (DMA) circuit configured to copy contents of an off-chip memory to an internal memory of a device. In some examples, the off-chip memory is external to the device. The example accelerator circuit also includes a decoder circuit configured to determine a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory. In some examples, the decoder circuit is also configured to direct the transaction to one of the off-chip memory or the internal memory based on whether a DMA copy of the region of the off-chip memory to the internal memory has completed.

公开(公告)号：US20250147752A1

公开(公告)日：2025-05-08

申请号：US18659615

申请日：2024-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Karthik Rajaraman ,  Mihir Narendra Mody ,  Prithvi Y.A. ,  Deepshikha Gusain ,  Niraj Nandan ,  Mohd Asif Farooqui

IPC: G06F8/654

Abstract: Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.

公开(公告)号：US12131504B2

公开(公告)日：2024-10-29

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: G06K9/00 ,  G06T1/20 ,  G06T7/90

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/10024 ,  G06T2207/20208

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US20240345870A1

公开(公告)日：2024-10-17

申请号：US18748423

申请日：2024-06-20

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: Systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (HTS). The data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. Each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. The task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. With this arrangement, the HTS couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.