公开(公告)号：US09202713B2

公开(公告)日：2015-12-01

申请号：US13181412

申请日：2011-07-12

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.

Abstract translation: 半导体器件具有具有活性表面的半导体管芯。 在活性表面上形成第一导电层。 在活性表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二绝缘层。 第二绝缘层的一部分被去除在第一导电层上，使得第二绝缘层的任何部分都不覆盖第一导电层。 在第一导电层和第一绝缘层和第二绝缘层上形成第二导电层。 第二导电层在第一导电层上延伸直到第一绝缘层。 或者，第二导电层在第一导电层的相对侧上横跨第一导电层延伸到第一绝缘层。 在第二导电层和第一绝缘层和第二绝缘层上形成第三绝缘层。

公开(公告)号：US09184103B2

公开(公告)日：2015-11-10

申请号：US13048771

申请日：2011-03-15

Applicant: Yaojian Lin ,  Haijing Cao ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/31 ,  H01L23/24 ,  H01L23/528 ,  H01L23/552 ,  H01L23/66 ,  H01L25/10 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L23/24 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/552 ,  H01L23/66 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer. The second conductive layer is electrically connected to the conductive pillars.

Abstract translation: 半导体器件包括第一导电层和设置在第一导电层之上并直接接触第一导电层的导电柱。 半导体器件包括安装到第一导电层的集成无源器件（IPD），使得IPD设置在导电柱之间。 IPD与第一导电层自对准，并且包括设置在第一基板上的金属 - 绝缘体 - 金属电容器和形成设置在第一基板上的电感器的缠绕导电层。 半导体器件包括安装在第一导电层上的分立电容器。 分立电容器电连接到导电柱之一。 半导体器件包括围绕IPD设置的密封剂，分立电容器和导电柱，设置在密封剂和导电柱上的第一绝缘层，以及设置在第一绝缘层上的第二导电层。 第二导电层电连接到导电柱。

公开(公告)号：US08999760B2

公开(公告)日：2015-04-07

申请号：US13492687

申请日：2012-06-08

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01L23/29 ,  H01L23/367 ,  H01L23/544

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/552 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24195 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K1/186 ,  H05K2201/09772 ,  H01L2924/01014 ,  H01L2924/05432 ,  H01L2924/0542 ,  H01L2924/0503 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract translation: 半导体器件具有形成在临时载体上的多个开口的导热层。 导热层包括非导电材料。 半导体管芯具有形成在管芯上的接触焊盘上的多个凸块。 半导体管芯安装在导热层上，使得凸块至少部分地设置在导热层的开口内。 将密封剂沉积在管芯和导热层上。 移除临时载体以暴露凸块。 在密封剂，半导体管芯和凸块之上形成第一互连结构。 凸块电连接到第一互连结构。 可以在半导体管芯上形成散热器或屏蔽层。 第二互连结构可以形成在密封剂之上并且通过形成在密封剂中的导电通孔电连接到第一互连结构。

公开(公告)号：US08900929B2

公开(公告)日：2014-12-02

申请号：US13426561

申请日：2012-03-21

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract translation: 半导体器件具有沉积在半导体管芯上的密封剂的半导体管芯。 在半导体管芯和密封剂上形成具有高拉伸强度和伸长率的第一绝缘层。 通过第一激光直接消融去除第一绝缘层的第一部分，以在第一绝缘层中形成多个开口。 这些开口部分地延伸穿过第一绝缘层或者进入密封剂。 通过第二激光直接烧蚀去除第一绝缘层的第二部分，以在第一绝缘层中形成多个沟槽。 在第一绝缘层的开口和沟槽中形成导电层。 在导电层上形成第二绝缘层。 通过第三激光直接烧蚀去除第二绝缘层的一部分。 在导电层上形成凸起。

公开(公告)号：US08900920B2

公开(公告)日：2014-12-02

申请号：US13207633

申请日：2011-08-11

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H05K1/18 ,  H01L25/16 ,  H01L23/50 ,  H05K3/46

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

公开(公告)号：US08895358B2

公开(公告)日：2014-11-25

申请号：US12557763

申请日：2009-09-11

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L21/00 ,  H01L29/40 ,  H01L23/538 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a PCB with a cavity formed in a first surface of the PCB. A stress compensating structure, such as an encapsulant or dummy die, is disposed in the cavity. An insulating layer is formed over the PCB and stress compensating structure. A portion of the insulating layer is removed to expose the stress compensating structure. A conductive layer is formed over the stress compensating structure. A solder masking layer is formed over the conductive layer with openings to the conductive layer. A semiconductor package is mounted over the cavity. The semiconductor package is a large array WLCSP. Bumps electrically connect the semiconductor package and conductive layer. The semiconductor package is electrically connected to the conductive layer. The CTE of the stress compensating structure is selected substantially similar to or matching the CTE of the semiconductor package to reduce stress between the semiconductor package and PCB.

Abstract translation: 半导体器件具有形成在PCB的第一表面中的空腔的PCB。 应力补偿结构，例如密封剂或模具，设置在空腔中。 在PCB上形成绝缘层和应力补偿结构。 绝缘层的一部分被去除以暴露应力补偿结构。 在应力补偿结构上形成导电层。 在导电层之上形成有焊料掩模层，具有到导电层的开口。 半导体封装安装在空腔上。 半导体封装是一个大阵列WLCSP。 冲击电路将半导体封装和导电层电连接。 半导体封装电连接到导电层。 应力补偿结构的CTE被选择为基本上类似于或匹配半导体封装的CTE，以减小半导体封装和PCB之间的应力。

公开(公告)号：US08810024B2

公开(公告)日：2014-08-19

申请号：US13429119

申请日：2012-03-23

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/04 ,  H01L23/24 ,  H01L21/00

CPC classification number: H01L23/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/28 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2924/00012

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract translation: 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。

公开(公告)号：US08624353B2

公开(公告)日：2014-01-07

申请号：US13311266

申请日：2011-12-05

Applicant: Yaojian Lin ,  Kai Liu ,  Kang Chen

Inventor： Yaojian Lin ,  Kai Liu ,  Kang Chen

IPC: H01L27/08 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H03H2001/0078 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯上形成第一电感器。 第二电感器形成在第一电感器上并与第一电感器对准。 在第一半导体管芯和第一和第二电感器上形成绝缘层。 导电桥形成在绝缘层之上并电连接在第二电感器和第一半导体管芯之间。 在一个实施例中，半导体器件具有第二半导体管芯，并且在第一和第二半导体管芯之间形成导电层。 在另一实施例中，在第一半导体管芯上形成电容器。 在另一个实施例中，绝缘层在第一半导体管芯的覆盖区之上具有第一厚度，并且第二厚度小于第一半导体管芯的覆盖区之外的第一厚度。

公开(公告)号：US08592311B2

公开(公告)日：2013-11-26

申请号：US13615308

申请日：2012-09-13

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/44

CPC classification number: H01L25/16 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2224/05599

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract translation: 半导体晶片包含其上形成有多个有源器件的衬底。 在基板上形成模拟电路。 模拟电路可以是电感，金属 - 绝缘体 - 金属电容或电阻。 电感由铜制成。 在衬底中形成贯穿衬底通孔（TSV）。 导电材料沉积在与模拟电路电接触的TSV中。 在与TSV电接触的衬底的背面上形成凸起下金属化层。 焊料材料沉积在UBM层上。 焊料材料被回流以形成焊料凸块。 在基板的顶表面上形成引线接合。 在TSV和UBM之间形成再分配层。 模拟电路通过TSV电连接到衬底背面的焊料凸块。

公开(公告)号：US08513812B2

公开(公告)日：2013-08-20

申请号：US13423832

申请日：2012-03-19

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/016 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/00

Abstract: An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures.

Abstract translation: IPD半导体器件具有形成在半导体管芯上并电连接的电容器。 密封剂沉积在电容器和半导体管芯周围。 第一互连结构通过形成第一导电层形成在密封剂的第一表面上，在第一导电层上形成第一绝缘层，并在第一绝缘层上形成第二导电层。 第二导电层具有形成在密封剂上方的部分，距离半导体管芯的覆盖区至少50微米，并被缠绕以用作电感器。 第二导电层的部分通过第一导电层与电容器电连接。 在密封剂的第二表面上形成第二互连结构。 在第一和第二互连结构之间的密封剂内形成导电柱。