公开(公告)号：US20020124153A1

公开(公告)日：2002-09-05

申请号：US10022421

申请日：2001-12-20

Inventor： Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrat

IPC: G06F015/00

CPC classification number: G06F12/0813 ,  G06F15/8015 ,  G11C7/1036

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract translation: 在单个集成电路上作为外部主器件的从器件的存储器组件包括RAM，一个或多个配置寄存器，数据格式化逻辑和相关联的控制逻辑。 存储器组件的行为，特别是突发传输格式的选择，可以通过一个或多个配置寄存器中的配置寄存器位进行控制。 具体地，基于由配置位指定的格式选择，控制逻辑确定RAM和外部主设备之间的数据传输的序列长度。 除了序列长度之外，在数据传输期间数据不会另外更改。

公开(公告)号：US06438017B1

公开(公告)日：2002-08-20

申请号：US09756953

申请日：2001-01-09

Applicant: Warren Kurt Howlett

Inventor： Warren Kurt Howlett

IPC: G11C1900

CPC classification number: G11C7/1036 ,  G11C7/1042 ,  G11C15/00 ,  G11C19/00

Abstract: M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Abstract translation: M个并行数据流被交织到一个串行比特流中，并被移入一个分段寄存器，所以所有数据流的位零都在第一位和第（X-1）位移位。 Mth数据流的所有位占据与具有每个宽度为X的M个存储器寄存器的目标存储器件互连的均匀间隔的非相邻存储器元件。存储器件的第M个存储器寄存器被寻址，同时将所有互连的位写入第M个存储器寄存器 在一个时钟周期内。 然后将比特流移位一个存储器元件，使得（M-1）个并行数据流的位占据互连存储器元件，寄存器地址递减，并且互连位同时写入第（M-1）个寄存器 。 该过程重复直到在M个时钟周期的经过时间内写入M个寄存器。 阅读基本上以相反的顺序发生。

公开(公告)号：US6373785B2

公开(公告)日：2002-04-16

申请号：US91657801

申请日：2001-07-30

Applicant: TOSHIBA KK

Inventor： TODA HARUKI ,  SAITO SHOZO ,  TOKUSHIGE KAORU

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/02 ,  G11C8/00

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit .for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal, provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

Abstract translation: 半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储器单元中由连续地址寻址的存储器单元，并将其输入激活状态; 用于对由指定电路指定的连续存储单元执行基于读出的控制的数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路 /从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且 指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得 控制存储单元组的存储器访问操作。

公开(公告)号：US06249481B1

公开(公告)日：2001-06-19

申请号：US09433338

申请日：1999-11-04

Applicant: Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C800

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

Abstract translation: 半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储单元中由连续地址寻址的存储器单元，并将其导入激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且 指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得 控制存储单元组的存储器访问操作。

公开(公告)号：US06188635B1

公开(公告)日：2001-02-13

申请号：US08488231

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US6161916A

公开(公告)日：2000-12-19

申请号：US396237

申请日：1999-09-15

Applicant: Bruce David Gibson ,  George Keith Parish

Inventor： Bruce David Gibson ,  George Keith Parish

IPC: B41J2/01 ,  B41J2/045 ,  B41J2/05 ,  B41J2/055 ,  B41J2/125 ,  B41J2/175 ,  B41J25/34 ,  B41J29/38 ,  G11C7/10 ,  G11C8/10 ,  G11C16/02 ,  B41J29/393

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: An ink jet print head identification system for providing print head identifying information to the electronics of an ink jet printer includes one or more parallel load, serial out, dynamic shift registers integrated into a print head chip having a plurality of address lines interconnecting the printer electronics and the print head electronics. The memory input of each shift register is electrically connected to a memory matrix that supplies digital bits of information to the shift register in response to receiving a decode signal function from the printer electronics. In a preferred embodiment, two of the address lines provide each of the registers with successive sequential clock signals to serially shift the bit of information received from the shift register's corresponding memory matrix to an output line where the print head identifying information is read by the printer electronics. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines.

Abstract translation: 一种用于向喷墨打印机的电子设备提供打印头识别信息的喷墨打印头识别系统包括集成到打印头芯片中的一个或多个并行负载串行输出动态移位寄存器，该打印头芯片具有多个地址线， 和打印头电子元件。 每个移位寄存器的存储器输入电连接到存储矩阵，该存储器矩阵响应于从打印机电子器件接收解码信号功能而将数字位信息提供给移位寄存器。 在优选实施例中，两个地址线向每个寄存器提供连续的顺序时钟信号，以将从移位寄存器的相应存储矩阵接收到的信息的位串行移位到打印头识别信息被打印机读取的输出行 电子产品。 本发明的实施例可以采用独立于可用地址线的数量的任意数量的移位寄存器和存储器矩阵。

公开(公告)号：US6112287A

公开(公告)日：2000-08-29

申请号：US24803

申请日：1993-03-01

Applicant: Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrat

Inventor： Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrat

IPC: G06F12/08 ,  G06F15/80 ,  G11C7/10 ,  G06F15/173

CPC classification number: G06F12/0813 ,  G06F15/8015 ,  G11C7/1036

Abstract: A multiprocessor system comprising a core memory (RAM), processing units (CPU.sub.1 -CPU.sub.j), each being provided with a cache memory (MCj), a directory (RG.sub.j) and a management processor (PG.sub.j); the core memory (RAM) is connected to an assembly of shift registers (RDM.sub.1 -RDM.sub.j) in such a way as to permit, in one cycle of the memory, a parallel transfer by reading or writing of data blocks; each cache memory (MC.sub.j) is connected to a shift register (RDP.sub.j)in such a way as to permit a parallel transfer by reading or writing of data blocks. An assembly of series connections, (LS.sub.1 -LS.sub.n) is provided between the assembly of memory shift registers and the assembly of processor shift registers to permit the transfer of data blocks between each pair of associated registers (RDM.sub.j -RDP.sub.j); the addresses of the data blocks can be transmitted between processor (CPU.sub.j) and the core memory (RAM) either by the series connections or by a common address bus (BUS A). The architecture according to the invention makes it possible to provide a large number of processing units while obtaining a high output from each processor.

Abstract translation: 包括核心存储器（RAM），处理单元（CPU1-CPUj），每个都具有高速缓冲存储器（MCj），目录（RGj）和管理处理器（PGj）的多处理器系统; 核心存储器（RAM）以这样的方式连接到移位寄存器（RDM1-RDMj）的组合，以便在存储器的一个周期中允许通过读或写数据块的并行传送; 每个高速缓存存储器（MCj）以允许通过读或写数据块的并行传送的方式连接到移位寄存器（RDPj）。 在组装存储器移位寄存器和组合处理器移位寄存器之间提供串联连接组件（LS1-LSn），以允许在每对相关寄存器（RDMj-RDPj）之间传输数据块; 数据块的地址可以通过串行连接或公共地址总线（BUS A）在处理器（CPUj）和核心存储器（RAM）之间传输。 根据本发明的架构使得可以在从每个处理器获得高输出的同时提供大量的处理单元。

公开(公告)号：US5815444A

公开(公告)日：1998-09-29

申请号：US995272

申请日：1997-12-19

Applicant: Yoshiji Ohta

Inventor： Yoshiji Ohta

IPC: G11C16/02 ,  G11C7/10 ,  G11C16/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/34

CPC classification number: G11C7/1036 ,  G11C16/0491

Abstract: There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array including a plurality of memory cells and shift registers and having a plurality of latch circuits connected in series are provided. The shift registers once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits and serially output the held data in the order in which the latch circuits are arranged. The latch circuits sense-amplify the data stored in the memory cells inside the memory cell array.

Abstract translation: 提供了能够减少访问时间并减少消耗电流的串行存取系统半导体存储装置。 提供包括多个存储单元和移位寄存器并且具有串联连接的多个锁存电路的存储单元阵列。 移位寄存器一旦在锁存电路中保持通过读操作中的位线从存储单元阵列1接收到的数据，并按照锁存电路布置的顺序串行输出保持的数据。 锁存电路对存储在存储单元阵列内的存储单元中的数据进行读出放大。

公开(公告)号：US5758037A

公开(公告)日：1998-05-26

申请号：US700157

申请日：1996-08-20

Applicant: Dale W. Schroeder

Inventor： Dale W. Schroeder

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1036

Abstract: A print controller with simplified video data storage operation. A single microprocessor provides a controller with a start address and a start command. The controller monitors a stream of digitized video data as it fills a two part serial register in a video random access memory ("VRAM"). As each successive part of the serial register is filled, the controller writes the contents of the filled part of the serial register to the VRAM. Upon receipt of a signal indicating the end of the image, digitized video data remaining in the register is written to the VRAM. Images are effectively streamed in, as opposed to the line by line storage of images used in known print controllers.

Abstract translation: 具有简化视频数据存储操作的打印控制器。 单个微处理器为控制器提供起始地址和起始命令。 控制器在视频随机存取存储器（“VRAM”）中填充两部分串行寄存器时监视数字化视频数据流。 当串行寄存器的每个连续部分被填充时，控制器将串行寄存器的填充部分的内容写入VRAM。 在接收到指示图像结束的信号时，将剩余在寄存器中的数字化视频数据写入VRAM。 图像被有效地流式传输，而不是逐行存储已知打印控制器中使用的图像。

公开(公告)号：US5717351A

公开(公告)日：1998-02-10

申请号：US620563

申请日：1996-03-22

Applicant: Masafumi Katsutani

Inventor： Masafumi Katsutani

IPC: G09G3/20 ,  G09G3/36 ,  G11C7/10 ,  G11C19/00 ,  H03K19/084

CPC classification number: G11C19/00 ,  G11C7/1036

Abstract: A start signal is given to an SP.sub.-- I/O buffer through a terminal SP1, and its pulse width is controlled by an SP control circuit. A selection signal SEL is given to a selector circuit so that the data shift direction of a bidirectional shift register is switched. When the shift direction is directed to the other side, the start signal is supplied from a terminal SP2 through an SP.sub.-- I/O buffer. When the shift operation is to be done from the terminal SP1 to the terminal SP2, the output of the 38th stage which precedes the final stage, namely, the 40th stage, by two stages is derived from the terminal SP2 as an input start signal for the succeeding driver, during a time period which is longer than one cycle of a clock signal CLK. According to this configuration, a cascade connection can be realized easily and surely even when a clock signal of a higher frequency is used.

Abstract translation: 通过端子SP1向SP-I / O缓冲器提供启动信号，其脉冲宽度由SP控制电路控制。 选择信号SEL被提供给选择器电路，使得双向移位寄存器的数据移位方向被切换。 当移位方向指向另一侧时，起始信号从终端SP2通过SP-I / O缓冲器提供。 当从终端SP1到终端SP2进行移位操作时，从终端SP2导出最终级，即第40级之前的第38级的输出，作为输入开始信号， 在后续驱动器中，在比时钟信号CLK的一个周期长的时间段内。 根据该结构，即使使用较高频率的时钟信号，也能容易且可靠地实现级联连接。