公开(公告)号：US08420452B2

公开(公告)日：2013-04-16

申请号：US13214076

申请日：2011-08-19

Applicant: Han-Ping Pu ,  Chien-Ping Huang

Inventor： Han-Ping Pu ,  Chien-Ping Huang

IPC: H01L21/4825

CPC classification number: H01L24/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

Abstract translation: 提供了一种引线框半导体封装及其制造方法。 基于引线框的半导体封装包括在其上注入多个第一和第二导电凸块的芯片以及具有多个引线的引线框架。 第一导电凸块被接合到引线以将芯片电连接到引线框架。 芯片，第一和第二导电凸块和引线框架由密封剂封装，第二导电凸块的底端和引线的底表面从密封剂暴露出来。 这允许第二导电凸块除了引线之外为芯片提供额外的输入/输出电连接。

公开(公告)号：US08241967B2

公开(公告)日：2012-08-14

申请号：US13032284

申请日：2011-02-22

Applicant: Chien-Ping Huang ,  Fu-Di Tang

Inventor： Chien-Ping Huang ,  Fu-Di Tang

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract translation: 提供了具有支撑结构的半导体封装及其制造方法。 通过将芯片电连接到形成在载体上的电触头，进行成型工艺。 形成在载体上的多个凹部填充有用于在模制过程中封装芯片的密封剂。 在移除载体之后，填充凹部的密封剂的一部分在密封剂的表面上形成向外突出的部分，使得半导体封装可以经由突出部分附接到外部装置。

公开(公告)号：US08183092B2

公开(公告)日：2012-05-22

申请号：US12829704

申请日：2010-07-02

Applicant: Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L21/00 ,  H01L21/46

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract translation: 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

公开(公告)号：US20110298126A1

公开(公告)日：2011-12-08

申请号：US12970126

申请日：2010-12-16

Applicant: Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/492 ,  H01L23/488 ,  H01L21/50

CPC classification number: H01L23/49582 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

Abstract translation: 制造无载体半导体封装的方法包括：半蚀刻金属载体以形成多个凹槽和多个金属柱，每个金属柱用作焊盘或管芯焊盘的位置; 用第一密封剂填充每个凹槽; 在金属柱上形成诸如镀银层或有机可焊保护层的抗氧化层; 并分别进行芯片接合，引线接合和模制工艺以形成封装芯片的第二密封剂。 凹槽被第一密封剂填充以增强第一密封剂和金属载体之间的粘合性，从而解决了具有弱和柔韧的铜板的传统问题，并避免了运输困难。 本发明消除了使用昂贵的金属作为抗蚀剂层以降低制造成本，并且还允许导电迹线被柔性地布置在金属载体上以增强电连接质量。

公开(公告)号：US20110287588A1

公开(公告)日：2011-11-24

申请号：US13195639

申请日：2011-08-01

Applicant: Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

Inventor： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC: H01L21/56

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.

Abstract translation: 公开了一种散热半导体封装结构及其制造方法。 该方法包括：在至少半导体芯片和封装单元上布置并电连接到芯片载体; 在所述封装单元的顶表面上设置有经由所述平坦部分具有平坦部分和支撑部分的散热元件; 在由散热元件的平坦部分和支撑部分形成的接收空间中接收封装单元和半导体芯片; 以及在芯片载体密封剂上形成以封装封装单元，半导体芯片和散热元件。 散热元件消散封装单元产生的热量，提供EMI屏蔽，防止封装单元与密封剂之间的分层，降低热阻，防止开裂。

公开(公告)号：US20110159643A1

公开(公告)日：2011-06-30

申请号：US12770059

申请日：2010-04-29

Applicant: Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/60 ,  H01L21/56

CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

Abstract translation: 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

公开(公告)号：US20110157851A1

公开(公告)日：2011-06-30

申请号：US12759117

申请日：2010-04-13

Applicant: Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

Inventor： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H05K7/02

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

Abstract translation: 封装结构包括具有第一密封剂和嵌入第一密封剂并暴露于第一密封剂的布线层的基体。 布线层具有多个导电迹线和多个第一电接触焊盘。 第一密封剂具有用于暴露第一电接触焊盘的开口，与布线层电连接的芯片，以及形成在基体上的用于覆盖芯片和布线层的第二密封剂，从而提供均匀的表面，以防止密封剂 芯片安装时开裂。

公开(公告)号：US20110156252A1

公开(公告)日：2011-06-30

申请号：US12859635

申请日：2010-08-19

Applicant: Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/49 ,  H01L21/00

CPC classification number: H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Abstract translation: 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及暴露管芯焊盘和迹线的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。

公开(公告)号：US20110143498A1

公开(公告)日：2011-06-16

申请号：US13032284

申请日：2011-02-22

Applicant: Chien-Ping Huang ,  Fu-Di Tang

Inventor： Chien-Ping Huang ,  Fu-Di Tang

IPC: H01L21/50

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract translation: 提供了具有支撑结构的半导体封装及其制造方法。 通过将芯片电连接到形成在载体上的电触头，进行成型工艺。 形成在载体上的多个凹部填充有用于在模制过程中封装芯片的密封剂。 在移除载体之后，填充凹部的密封剂的一部分在密封剂的表面上形成向外突出的部分，使得半导体封装可以经由突出部分附接到外部装置。

公开(公告)号：US20110070728A1

公开(公告)日：2011-03-24

申请号：US12956393

申请日：2010-11-30

Applicant: Chun-Chi Ke ,  Chien-Ping Huang

Inventor： Chun-Chi Ke ,  Chien-Ping Huang

IPC: H01L21/768

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

Abstract translation: 提出了具有导电凸块的半导体器件及其制造方法。 该制造方法包括以下步骤：在具有焊盘和形成在其上的钝化层的基板上形成第一金属层，并将其电连接到焊盘; 在第一金属层的暴露部分上施加第二覆盖层; 随后在第二覆盖层上形成第二金属层，并将其电连接到第一金属层的暴露部分; 施加第三覆盖层，以及形成用于暴露第二金属层的部分的开口以在其上形成具有金属支座和焊料材料的导电凸块。 覆盖层和金属层可以提供缓冲效果，用于有效地吸收施加在导电凸块上的热应力，以防止由UBM层引起的分层。