公开(公告)号：US10691520B2

公开(公告)日：2020-06-23

申请号：US15942186

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07 ,  G06F11/14

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

公开(公告)号：US10534034B2

公开(公告)日：2020-01-14

申请号：US15039515

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Daniel S. Froelich ,  Debendra Das Sharma

IPC: G01R31/317 ,  H04B3/46 ,  G06F11/22 ,  G01R31/3177 ,  G06F11/36 ,  H01L21/66 ,  G06F11/00 ,  G06F13/16 ,  G01R31/28 ,  G01R31/327 ,  G06F11/07

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

公开(公告)号：US20190041898A1

公开(公告)日：2019-02-07

申请号：US15920249

申请日：2018-03-13

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US10198394B2

公开(公告)日：2019-02-05

申请号：US15283310

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US10191877B2

公开(公告)日：2019-01-29

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F1/10

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20180225233A1

公开(公告)日：2018-08-09

申请号：US15942160

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42

Abstract: Data is accessed from a particular register first device that is connected to a second device via a link that includes at least one retimer device. The particular register corresponds to requests to be sent in in-band transactions with the retimer, and the data corresponds to a particular transaction with the retimer. At least one ordered set is generated at the first device to comprise a subset of bits encoded with the data, where the ordered set with the encoded subset of bits is to be sent on the link and the subset of bits are to be processed by the retimer in the particular transaction.

公开(公告)号：US20180225167A1

公开(公告)日：2018-08-09

申请号：US15942186

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07 ,  G06F11/14

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

公开(公告)号：US20180191374A1

公开(公告)日：2018-07-05

申请号：US15851747

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: H03M13/11 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20180181502A1

公开(公告)日：2018-06-28

申请号：US15387802

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Debendra Das Sharma ,  Venkatraman Iyer ,  Tao Liang

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.