公开(公告)号：US10461182B1

公开(公告)日：2019-10-29

申请号：US16021772

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  James Robert Todd ,  Binghua Hu ,  Xiaoju Wu ,  Stephanie L. Hilbun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

公开(公告)号：US09929140B2

公开(公告)日：2018-03-27

申请号：US14713785

申请日：2015-05-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Binghua Hu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/762 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/06 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/1095

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US09754929B2

公开(公告)日：2017-09-05

申请号：US14311205

申请日：2014-06-20

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Md Iqbal Mahmud

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/747 ,  H01L29/66 ,  H01L29/45 ,  H01L29/74 ,  H01L29/06

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/66386 ,  H01L29/7436 ,  H01L29/747

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

公开(公告)号：US20170213895A1

公开(公告)日：2017-07-27

申请号：US15406913

申请日：2017-01-16

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/167 ,  H01L21/324 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/402 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32 ,  H01L21/324 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US20170213893A1

公开(公告)日：2017-07-27

申请号：US15406891

申请日：2017-01-16

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L21/225 ,  H01L21/02 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L21/266 ,  H01L29/78

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US09673273B2

公开(公告)日：2017-06-06

申请号：US15175192

申请日：2016-06-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu ,  Henry Litzmann Edwards

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/167 ,  H01L21/74

CPC classification number: H01L29/0623 ,  H01L21/02164 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324 ,  H01L21/74 ,  H01L29/0646 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

公开(公告)号：US09659934B2

公开(公告)日：2017-05-23

申请号：US14725869

申请日：2015-05-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L29/76 ,  H01L29/775 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/12 ,  H01L27/15

CPC classification number: H01L27/092 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/15 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/122 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/7836

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

公开(公告)号：US09658110B1

公开(公告)日：2017-05-23

申请号：US14955251

申请日：2015-12-01

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: G01J5/00 ,  G01J5/12 ,  G01J5/34

CPC classification number: G01J5/12 ,  G01J5/34 ,  G01J2005/123 ,  G01J2005/345

Abstract: A thermal sensor device using a combination of thermopile and pyroelectric sensors is disclosed. The combination is achieved in a process flow that includes ferroelectric materials, which may be used as a pyroelectric sensor, and p-poly/n-poly for thermopiles. The combination retains the sensitivity and accuracy of the thermopile sensor and speed of pyroelectric sensors. The combination provides lower noise than individual thermopile sensors and results in a higher signal-to-noise ratio.

公开(公告)号：US09508707B2

公开(公告)日：2016-11-29

申请号：US14630727

申请日：2015-02-25

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/06 ,  H01L29/739 ,  H01L21/8249 ,  H03K17/66 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/66 ,  H01L29/735 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8228 ,  H01L21/8249 ,  H01L27/082 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393 ,  H03K17/66

Abstract: A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal.

Abstract translation: 半导体器件包括量子阱调制双极结型晶体管（QW调制BJT），其具有在基极中具有可调制量子阱的面积的基极。 QW调制的BJT包括量子阱（QW）控制节点，其能够调制量子阱的能级的数量和水平。 重组位点与至少25平方纳米的接触面积邻接量子阱的区域。 可以通过向发射器提供诸如接地的参考节点和到集电极的电源来操作半导体器件。 向栅极提供偏置电压以形成量子阱，并且向栅极提供信号电压，使得集电极电流包括随信号而变化的分量。

公开(公告)号：US09373615B2

公开(公告)日：2016-06-21

申请号：US14531751

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/66 ,  H01L27/02 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/0664 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/067 ,  H01L29/0649 ,  H01L29/41708 ,  H01L29/45

Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

Abstract translation: 晶体管包括第一导电类型的发射极，第二导电类型的基极，第一导电类型的集电极和横向抑制二极管的阴极。 发射极设置在晶体管的顶表面并被配置为从外部源接收电流。 基座被配置为将电流从集电器传导到发射极。 基极设置在晶体管的顶表面，并且在发射极和集电极之间。 收集器被配置为从基地吸引和收集少数载体。 第一导电类型的阴极由基极围绕并且设置在发射极和集电极之间，并且阴极被配置为抑制少数载流子从基极到集电极的横向流动。