公开(公告)号：US07882166B2

公开(公告)日：2011-02-01

申请号：US10781878

申请日：2004-02-20

Applicant: Kiyoshi Shinomiya

Inventor： Kiyoshi Shinomiya

IPC: G06F15/16

CPC classification number: H04L29/06 ,  G06F12/1036 ,  H04L67/1097 ,  H04L69/329

Abstract: A data transfer method for a network system wherein a plurality of computers are connected to each other through a switched network is improved in terms of the TLB hit ratio. Each of the computers includes a main storage device, a processor for issuing a communication process command and a communication device for processing the communication command from the processor and communicating with another one of the computers through a switched network. The communication device includes a transmission section and a reception section each of which includes a TLB for retaining a plurality of TLB entries. When a communication command including information of that one of the computers which is a sending source is issued from the processor, the reception section determines that one of the TLB entries which is to be used in accordance with the computer of the sending source.

Abstract translation: 根据TLB命中率，提高了通过交换网络将多个计算机彼此连接的网络系统的数据传输方法。 每个计算机包括主存储装置，用于发出通信处理命令的处理器和用于处理来自处理器的通信命令并通过交换网络与另一计算机通信的通信装置。 通信装置包括发送部分和接收部分，每个发送部分和接收部分都包括用于保留多个TLB条目的TLB。 当从处理器发出包括作为发送源的计算机的信息的通信命令时，接收部分根据发送源的计算机确定要使用的一个TLB条目。

公开(公告)号：US20100321397A1

公开(公告)日：2010-12-23

申请号：US12489954

申请日：2009-06-23

Applicant: Boris Ginzburg

Inventor： Boris Ginzburg

IPC: G09G5/39

CPC classification number: G06T1/60 ,  G06F3/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/656 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。 该设备可以连接到具有主机处理器和主机内存的主机。 两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。 描述和要求保护其他实施例。

公开(公告)号：US20100287356A1

公开(公告)日：2010-11-11

申请号：US12437628

申请日：2009-05-08

Applicant: George R. Cameron ,  Blake A. Jones ,  Rodrick I. Evans ,  Michael E. Corcoran

Inventor： George R. Cameron ,  Blake A. Jones ,  Rodrick I. Evans ,  Michael E. Corcoran

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

Abstract: A method for loading shared libraries. The method includes receiving an indication of a requirement to load the shared library into the virtual memory and determining that the shared library is a candidate for using shared large pages. Further, the method includes, in response to the determination, storing a text section of the shared library in a shared large page of the virtual memory and storing a data section of the shared library in a page of the virtual memory, where the virtual memory is mapped to a physical memory of the computer, where, within an address space of the virtual memory, a starting address of the text section of the shared library is separated from a starting address of the data section of the shared library by a predefined distance, and where the predefined distance is larger than a size of the large page.

Abstract translation: 一种加载共享库的方法。 该方法包括接收将共享库加载到虚拟存储器中并且确定共享库是使用共享大页面的候选者的要求的指示。 此外，该方法响应于确定，将共享库的文本部分存储在虚拟存储器的共享大页面中，并且将共享库的数据部分存储在虚拟存储器的页面中，其中虚拟存储器 被映射到计算机的物理存储器，其中在虚拟存储器的地址空间内，共享库的文本部分的起始地址与共享库的数据部分的起始地址以预定距离分开 ，并且其中预定距离大于大页面的大小。

公开(公告)号：US07822942B2

公开(公告)日：2010-10-26

申请号：US12054538

申请日：2008-03-25

Applicant: Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

Inventor： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC: G06F13/00

CPC classification number: G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Abstract translation: 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

公开(公告)号：US20100205347A1

公开(公告)日：2010-08-12

申请号：US12766430

申请日：2010-04-23

Applicant: Naoya Hattori ,  Toshiomi Moriki ,  Yuji Tsushima

Inventor： Naoya Hattori ,  Toshiomi Moriki ,  Yuji Tsushima

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1036 ,  G06F9/45537 ,  G06F12/1009 ,  G06F12/109

Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.

Abstract translation: 当在虚拟机上运行的客户操作系统更新访客页表（PT）地址时，提供一种消除虚拟机监视器（VMM）执行的阴影PT操作的冗余的方法。 VMM将多个阴影PT与客户PT相关联，并将其关系分配给内存。 当检测到客户PT地址的更新时，VMM搜索与更新的客户PT相对应的影子PT。 如果相关联的阴影PT存在，则VMM将省略重写阴影PT，并将阴影PT的地址与中央处理单元（CPU）注册。 如果相关联的阴影PT不存在，则VMM分配存储器，创建阴影PT，向CPU注册创建的阴影PT的地址，并记录更新的客户PT与生成的阴影PT之间的关系。

公开(公告)号：US20100191923A1

公开(公告)日：2010-07-29

申请号：US12361943

申请日：2009-01-29

Applicant: Charles J. Archer ,  James E. Carey ,  Philip J. Sanders

Inventor： Charles J. Archer ,  James E. Carey ,  Philip J. Sanders

IPC: G06F12/00

CPC classification number: G06F12/1036

Abstract: Methods, apparatus, and products for data processing in a computing environment including allocating, by an operating system for an application, a virtual address spaces with each virtual address space mapped to a same physical address space and each virtual address space associated with an operation; receiving, from the application, an instruction to store a value in a specific virtual address, the specific virtual address contained within one of the allocated virtual address spaces; identifying a physical address associated with the specific virtual address; performing, with the value and the contents of the identified physical address, the operation associated with the virtual address space containing the specific virtual address; and storing a result of the operation in the identified physical address.

Abstract translation: 用于在计算环境中进行数据处理的方法，装置和产品，包括由操作系统为应用分配映射到相同物理地址空间的每个虚拟地址空间的虚拟地址空间以及与操作相关联的每个虚拟地址空间; 从所述应用程序接收用于存储特定虚拟地址中的值的指令，所述特定虚拟地址包含在所分配的虚拟地址空间之一内; 识别与所述特定虚拟地址相关联的物理地址; 使用所识别的物理地址的值和内容执行与包含特定虚拟地址的虚拟地址空间相关联的操作; 以及将所述操作的结果存储在所识别的物理地址中。

公开(公告)号：US20100161929A1

公开(公告)日：2010-06-24

申请号：US12338234

申请日：2008-12-18

Applicant: George Nation ,  Robert E. Ober

Inventor： George Nation ,  Robert E. Ober

IPC: G06F12/02

CPC classification number: G06F12/0284 ,  G06F9/5016 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/2022 ,  G06F2212/401 ,  G06F2212/656

Abstract: Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide methods for configuring a shared main memory region. The methods include providing a memory appliance that includes a randomly accessible bank of memory and a memory controller that is operable to maintain information in relation to a first virtual machine and a second virtual machine. The methods further include receiving a request to allocate a first portion of the bank of memory to the first virtual machine, and receiving a request to allocate a second portion of the bank of memory to the second virtual machine. The first portion of the bank of memory is identified as accessible to the first virtual machine, and the second portion of the bank of memory is identified as accessible to the second virtual machine.

Abstract translation: 本发明的各种实施例提供了用于在多个虚拟机之间提供存储器访问的系统和方法。 例如，本发明的各种实施例提供了用于配置共享主存储器区域的方法。 所述方法包括提供包括可随机访问的存储器组的存储设备和可操作以维护与第一虚拟机和第二虚拟机相关的信息的存储器控​​制器。 所述方法还包括接收向所述第一虚拟机分配所述存储体的第一部分的请求，以及接收将所述存储体的第二部分分配给所述第二虚拟机的请求。 存储器组的第一部分被识别为对于第一虚拟机可访问，并且存储器组的第二部分被识别为可访问第二虚拟机。

公开(公告)号：US20100161875A1

公开(公告)日：2010-06-24

申请号：US12633299

申请日：2009-12-08

Applicant: Xiao Tao Chang ,  Huayong Wang ,  Kun Wang ,  Yu Zhang

Inventor： Xiao Tao Chang ,  Huayong Wang ,  Kun Wang ,  Yu Zhang

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/00

CPC classification number: G06F12/1036 ,  G06F9/4552 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

Abstract: A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space. The simulator further includes an update tracing device configured for, in response to the update to the guest translation look-aside buffer, perform the update to the host translation look-aside buffer. Also disclosed is a method for running a guest program in a host.

Abstract translation: 公开了一种用于在主机中运行访客程序的模拟器和模拟方法。 模拟器包括：配置用于设置主机中的管理程序页表的内容的初始化设备，将客户物理地址空间映射到主机物理地址空间的管理程序页表。 仿真器还包括被配置为使用程序逻辑地址来执行代码转换中的存储器访问的二进制翻译装置。 所述模拟器还包括未命中处理装置，其被配置为通过处理由所述翻译代码的执行而导致的主机翻译后备缓冲器中的未命中来更新客体翻译后备缓冲器，作为所述访客翻译后备缓冲器中的未命中， 其中所述主机翻译后备缓冲器被配置为缓冲条目以将访客程序逻辑地址空间中的地址映射到所述访客物理地址空间中的地址。 所述模拟器还包括更新跟踪装置，所述更新跟踪装置被配置为响应于所述客户端翻译后备缓冲器的更新，执行对所述主机翻译后备缓冲器的更新。 还公开了一种在主机中运行客座程序的方法。

公开(公告)号：US07739477B2

公开(公告)日：2010-06-15

申请号：US11733520

申请日：2007-04-10

Applicant: Jeffrey Powers Bradford ,  Jason Nathaniel Dale ,  Kimberly Marie Fernsler ,  Timothy Hume Heil ,  James Allen Rose

Inventor： Jeffrey Powers Bradford ,  Jason Nathaniel Dale ,  Kimberly Marie Fernsler ,  Timothy Hume Heil ,  James Allen Rose

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/1036 ,  G06F2212/652

Abstract: Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

Abstract translation: 页面大小预测用于预测由存储器访问指令访问的存储器页面的页面大小，使得可以使用预测的页面大小来访问地址转换数据结构。 通过这样做，地址转换数据结构可以以有效的方式支持多个页面大小，并且在关键路径中设置少量额外的电路用于地址转换，从而提高性能。

公开(公告)号：US07734892B1

公开(公告)日：2010-06-08

申请号：US11096922

申请日：2005-03-31

Applicant: Guillermo J. Rozas ,  Nathan Laredo

Inventor： Guillermo J. Rozas ,  Nathan Laredo

IPC: G06F21/00

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/145 ,  G06F2009/45583

Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application on a host computer system, executing a first virtual machine application within a first virtual machine, and executing a second virtual machine application within a second virtual machine. A plurality of TLB (translation look aside buffer) entries for the first virtual machine application and the second machine application are stored within a TLB of the host computer system. At least one of the plurality of TLB entries is a global TLB entry.

Abstract translation: 一种为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法。 该方法包括在主计算机系统上执行主机应用，在第一虚拟机内执行第一虚拟机应用，以及在第二虚拟机内执行第二虚拟机应用。 用于第一虚拟机应用和第二机器应用的多个TLB（转换后备缓冲器）条目被存储在主计算机系统的TLB内。 多个TLB条目中的至少一个是全局TLB条目。