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    Variable clock divider
    142.
    发明授权
    Variable clock divider 有权

    公开(公告)号：US11749324B2

    公开(公告)日：2023-09-05

    申请号：US17935016

    申请日：2022-09-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yutaka Uemura

    IPC: G11C7/22 ,  G11C7/10 ,  H03K23/52 ,  G11C29/10 ,  H03K23/00

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1036 ,  G11C7/1045 ,  G11C7/1087 ,  G11C29/10 ,  H03K23/002 ,  H03K23/52

    Abstract: Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

    SIMULATING ACCESS LINES
    147.
    发明申请
    SIMULATING ACCESS LINES 审中-公开

    公开(公告)号：US20180286468A1

    公开(公告)日：2018-10-04

    申请号：US15997389

    申请日：2018-06-04

    Applicant: Micron Technology, Inc.

    Inventor： Jeremiah J. Willcock

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/08 ,  G11C11/4096 ,  G11C5/06 ,  G11C19/00

    CPC classification number: G11C7/065 ,  G11C5/066 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1036 ,  G11C7/1063 ,  G11C7/1069 ,  G11C11/4096 ,  G11C19/00

    Abstract: Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.

    Memory device
    148.
    发明授权
    Memory device 有权

    公开(公告)号：US10002667B1

    公开(公告)日：2018-06-19

    申请号：US15612734

    申请日：2017-06-02

    Applicant: SK hynix Inc.

    Inventor： Sang-Oh Lim ,  Jong-Tai Park

    IPC: G11C16/08 ,  G11C16/10

    CPC classification number: G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C19/287

    Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.

    Simulating access lines
    149.
    发明授权
    Simulating access lines 有权

    公开(公告)号：US09990966B2

    公开(公告)日：2018-06-05

    申请号：US15645238

    申请日：2017-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Jeremiah J. Willcock

    IPC: G11C7/08 ,  G11C7/06 ,  G11C11/4096 ,  G11C7/10 ,  G11C5/06 ,  G11C19/00

    CPC classification number: G11C7/065 ,  G11C5/066 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1036 ,  G11C7/1063 ,  G11C7/1069 ,  G11C11/4096 ,  G11C19/00

    Abstract: Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.

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