公开(公告)号：US20180025768A1

公开(公告)日：2018-01-25

申请号：US15213755

申请日：2016-07-19

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush

IPC: G11C11/4091 ,  G11C29/52 ,  G06F11/10 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G06F11/1048 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/52 ,  G11C2029/0411

Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.

公开(公告)号：US09837133B1

公开(公告)日：2017-12-05

申请号：US15177088

申请日：2016-06-08

Applicant: Altera Corporation

Inventor： Bruce B. Pedersen

IPC: G06F12/06 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/06 ,  G11C7/10 ,  G11C7/1036 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18

Abstract: Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block RAM such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address is provided to the block RAM and the address increment signal is asserted, data may be read from location instead of , where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.

公开(公告)号：US20170309316A1

公开(公告)日：2017-10-26

申请号：US15591899

申请日：2017-05-10

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G06F13/16 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F13/1663 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/005 ,  G11C2211/5641

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

公开(公告)号：US09786338B2

公开(公告)日：2017-10-10

申请号：US15238186

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/30 ,  G11C7/10

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

公开(公告)号：US09741399B2

公开(公告)日：2017-08-22

申请号：US15060222

申请日：2016-03-03

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

公开(公告)号：US09734876B2

公开(公告)日：2017-08-15

申请号：US14599892

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/30 ,  G06F9/34 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

公开(公告)号：US09508455B2

公开(公告)日：2016-11-29

申请号：US14595252

申请日：2015-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C7/10 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50016 ,  G11C7/02 ,  G11C7/1036 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427 ,  G11C16/3459 ,  G11C19/00 ,  G11C29/86 ,  G11C2211/5621

Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.

Abstract translation: 存储器件的操作方法包括以下步骤：第一页缓冲器接收要被编程到存储器单元的第一存储器单元中的第一输入数据; 第二页缓冲器接收要编程到存储器单元的第二存储单元中的第二输入数据; 并且第一页缓冲器根据第一和第二输入数据确定是否移位用于第一输入数据的程序验证（PV）电压。

公开(公告)号：US09312020B2

公开(公告)日：2016-04-12

申请号：US14686092

申请日：2015-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C16/00 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C7/10

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

Abstract translation: 操作存储器件的方法包括将增加的感测电压施加到多个存储器单元，其中多个存储器单元中的存储单元每个存储表示两位或多位数据的数据状态。 所述方法还包括响应于增加的感测电压达到特定水平，启动对多个存储器单元中的每个存储单元的特定数据数据的数据值的传送，同时继续将增加的感测电压施加到多个存储单元 的记忆细胞。

公开(公告)号：US20160077999A1

公开(公告)日：2016-03-17

申请号：US14950017

申请日：2015-11-24

Applicant: III HOLDINGS 2, LLC

Inventor： Prashant R. Chandra ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Niall Joseph Dalton

IPC: G06F15/173 ,  G11C7/10 ,  G06F13/16 ,  G11C21/00

CPC classification number: G06F12/00 ,  G06F9/54 ,  G06F12/0223 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/17375 ,  G11C7/1036 ,  G11C7/1072 ,  G11C21/00 ,  Y02D10/14

Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.

Abstract translation: 数据处理节点具有节点间消息传递模块，其包括多个寄存器组，每组寄存器定义GET / PUT上下文的实例和多个数据处理核心，每个数据处理核心耦合到节点间消息传递模块。 每个数据处理核心包括映射功能，用于将多个用户级过程中的每一个映射到寄存器组中的不同的一个，从而映射到相应的GET / PUT上下文实例。 将每个用户级进程映射到不同的一组寄存器使得特定的一个用户级进程能够利用其相应的GET / PUT上下文实例来执行GET / PUT动作到不同的环形缓冲区 数据处理节点通过结构耦合到数据处理节点，而不涉及任何一个数据处理核心的操作系统。

公开(公告)号：US20150371690A1

公开(公告)日：2015-12-24

申请号：US14722291

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Alexander Khazin

IPC: G11C7/10 ,  G06F13/28 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC classification number: G11C7/1075 ,  G06F13/287 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G11C7/1036

Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

Abstract translation: 公开了存储介质之间的时间受限的数据复制。 当电子设备进行实时操作时，在某些时间限制内可能需要将多个数据块从一个存储介质复制到另一个存储介质。 在这方面，数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组，同时数据端口仍然被复制的多个寄存器的控制。 通过在时间限制内复制多个寄存器，可以防止数据端口中的操作中断，并减少与寄存器复制操作相关联的带宽开销。