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公开(公告)号：US20190181764A1
公开(公告)日：2019-06-13
申请号：US15835234
申请日：2017-12-07
Applicant: Silicon Laboratories Inc.
Inventor： Krishna Pentakota , Mohammad Al-Shyoukh , Stefan N. Mastovich
IPC: H02M3/335 , G01R19/18 , H01L21/48 , H01L23/498 , H01L23/64 , H01L23/66 , H03F3/213 , H03F3/195 , H02M7/537
Abstract: An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.
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公开(公告)号：US20190178937A1
公开(公告)日：2019-06-13
申请号：US15836363
申请日：2017-12-08
Applicant: Silicon Laboratories Inc.
Inventor： Huanhui Zhan , Krishna Pentakota , Stefan N. Mastovich
IPC: G01R31/317 , G01R31/316
Abstract: An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.
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公开(公告)号：US20190171241A1
公开(公告)日：2019-06-06
申请号：US15833515
申请日：2017-12-06
Applicant: Silicon Laboratories Inc.
Inventor： MOHAMED ELSAYED , SCOTT D. WILLINGHAM
Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.
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公开(公告)号：US10312955B1
公开(公告)日：2019-06-04
申请号：US15859894
申请日：2018-01-02
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong
Abstract: A method compensates for a frequency error in a communications system. The method includes detecting a received preamble sequence in a received signal. The received preamble sequence is detected based on a plurality of power estimates corresponding to a plurality of frequency bins of a received frequency domain signal and a plurality of relative phase errors corresponding to the plurality of frequency bins of the received frequency domain signal. The method includes determining the frequency error using the received preamble sequence. The method includes adjusting the receiver based on the frequency error.
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公开(公告)号：US10296026B2
公开(公告)日：2019-05-21
申请号：US14918651
申请日：2015-10-21
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Vaibhav Karkare
Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.
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Patent Agency Ranking
公开(公告)号：US10289840B2
公开(公告)日：2019-05-14
申请号：US15612841
申请日：2017-06-02
Applicant: Silicon Laboratories Inc.
Inventor： Javier Elenes , Sebastian Ahmed , Lars Lydersen
Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.
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167.发明授权公开(公告)号：US10256858B1
公开(公告)日：2019-04-09
申请号：US15707306
申请日：2017-09-18
Applicant: Silicon Laboratories Inc.
Inventor： Alexander August Arthur Hakkola
Abstract: In one embodiment, an apparatus includes: a first radio receiver to receive and downconvert a first radio frequency (RF) signal to a first digital signal; a second radio receiver to receive and downconvert a second RF signal to a second digital signal; a correlation circuit to receive the first and second digital signals and determine a correlation between the first and second digital signals; a weight calculation circuit to determine a first weight value and a second weight value based at least in part on the correlation; and a combiner circuit to combine the first and second digital signals according to the first and second weight values.
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公开(公告)号：US10254176B2
公开(公告)日：2019-04-09
申请号：US14246461
申请日：2014-04-07
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Jeffrey L. Sonntag
Abstract: An apparatus includes a thermistor having a variable resistance with a first dependence on absolute temperature. The apparatus includes a reference resistor having a resistance with a second dependence on absolute temperature, the second dependence being less than or having opposite polarity to the first dependence. The reference resistor includes a switched-capacitor circuit. The apparatus includes a node coupled between the thermistor and the reference resistor. The node is configured to provide a signal indicative of absolute temperature based on the variable resistance and the reference resistance. The signal may be strain-invariant, proportional to a reference voltage, and indicative of a ratio of the variable resistance to the reference resistance. The apparatus may include a feedback circuit configured to maintain the node at a predetermined voltage level.
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公开(公告)号：US20190097842A1
公开(公告)日：2019-03-28
申请号：US15716999
申请日：2017-09-27
Applicant: Silicon Laboratories Inc.
Inventor： DeWitt Clinton Seward , Greg Hodgson , Clay Daigle , Preston Fick , John Hemmick
Abstract: A system and method for allowing legacy devices to operate on an IPv4 network is disclosed. The system includes a gateway device to interface between IPv4 devices and legacy devices. In some embodiments, the gateway device has a plurality of network interfaces to communicate with these legacy devices. The gateway device discovers the legacy devices that it can communicate with. The gateway device then enumerates these legacy devices in a manner that allows them to be accessible to the IPv4 device. In certain embodiments, the gateway enumerates each legacy device as a port on its IPv4 address.
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公开(公告)号：US20190094302A1
公开(公告)日：2019-03-28
申请号：US15713178
申请日：2017-09-22
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: G01R31/3185 , G05F1/10 , G01R31/319
Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
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