公开(公告)号：US09164139B2

公开(公告)日：2015-10-20

申请号：US13962233

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee Shin ,  Young Man Ahn ,  Seung Mo Jung ,  You Keun Han ,  Sang Jhun Hwang

IPC: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G11C11/4096 ,  G11C5/04 ,  G11C29/12 ,  G01R31/27 ,  G11C7/10 ,  G11C29/02 ,  G11C29/14 ,  G11C29/04 ,  G11C29/40 ,  G06F13/28 ,  G11C11/406 ,  H03M13/00 ,  H03M7/40 ,  G06F17/50

CPC classification number: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G01R31/27 ,  G06F13/28 ,  G06F17/5054 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1036 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/0401 ,  G11C2029/4002 ,  H03M7/40 ,  H03M13/00

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract translation: 存储器件包括存储单元阵列和数据输入/输出电路。 存储单元阵列包括连接到多个位线和多个字线的多个存储单元。 数据输入/输出电路被配置为从存储器件的外部数据引脚接收数据，通过电耦合到多个位线的多个输入/输出线将接收到的数据输出到存储单元阵列，从多个位线读取数据 通过多个输入/输出线的存储单元阵列，并通过外部数据引脚输出读取的数据。 对于每个外部数据引脚，数据输入/输出电路被配置为将在外部数据引脚处接收的数据输出到相应的输入/输出线。 响应于包含在接收数据中的一组位的位值来选择相应的输入/输出线。

公开(公告)号：US09093336B2

公开(公告)日：2015-07-28

申请号：US13765208

申请日：2013-02-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gopalkrishna Ullal Nayak ,  Matthew Craig Bullock

IPC: H01L21/66 ,  G01R31/26 ,  H01L23/58 ,  H01L29/10

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C29/04 ,  H01L22/14 ,  H01L22/20

Abstract: In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.

Abstract translation: 在用于电子设备的半导体芯片中，可编程修剪代码与默认修剪代码无关。 通过选择默认修剪代码或可编程修剪代码来生成输出修剪代码。 通过在至少一个半导体芯片的制造期间通过在金属互连层中根据第一金属布局形成金属互连来设定多个半导体芯片的默认修剪代码。 通过在后续半导体芯片的制造期间通过在金属互连层中根据第二金属布局形成金属互连来复位默认修剪代码。

公开(公告)号：US20150187395A1

公开(公告)日：2015-07-02

申请号：US14660219

申请日：2015-03-17

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/10 ,  G11C5/06 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Abstract translation: 本公开包括与数据移位相关的装置和方法。 示例性设备包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移动阵列中的数据，而不经由阵列的输入/输出线传送数据。

公开(公告)号：US20150127856A1

公开(公告)日：2015-05-07

申请号：US14587712

申请日：2014-12-31

Applicant: Altera Corporation

Inventor： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

IPC: G06F13/42 ,  G06F13/40

CPC classification number: H04L25/03866 ,  G06F3/00 ,  G06F5/00 ,  G06F7/58 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/4221 ,  G06F13/4282 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/285 ,  H04L9/00

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract translation: 公开了与可配置加扰电路相关的各种结构和方法。 实施例可以被配置为支持多个协议中的一个。 一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。 一些实施例可配置为选择加扰器类型。 一些实施例可配置为适应多个协议特定的加扰多项式之一。 一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。 在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

公开(公告)号：US08938590B2

公开(公告)日：2015-01-20

申请号：US12253967

申请日：2008-10-18

Applicant: Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/34

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract translation: 提供了系统和方法来管理对寄存器的访问。 在一个实施例中，系统可以包括处理器和多个寄存器。 处理器和多个寄存器可以集成到单个设备中，或者可以在单独的设备中。 多个寄存器可以包括可由处理器直接访问的第一组寄存器和不能由处理器直接访问的第二组寄存器。 然而，第二组寄存器可以由处理器经由第一组寄存器间接访问。 在一个实施例中，第一组寄存器可以包括用于从第二组寄存器中选择寄存器组的寄存器和用于选择寄存器组中的特定地址的寄存器，以允许处理器间接访问寄存器组的寄存器 第二集

公开(公告)号：US20150006848A1

公开(公告)日：2015-01-01

申请号：US13931008

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。 该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。 该操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。

公开(公告)号：US08897080B2

公开(公告)日：2014-11-25

申请号：US13630278

申请日：2012-09-28

Applicant: Wanfang Tsai

Inventor： Wanfang Tsai

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1036 ,  G11C7/1087 ,  G11C2207/107

Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.

Abstract translation: 提出了可用于固定或可变速率串行到并行数据转换的移位寄存器结构。 在1到N转换中，在传输到（N×m）范围的并行数据总线之前，数据从m位串行数据总线接收并被加载到N宽m锁存器中。 基于关于N m位宽数据单元如何被忽略的信息，数据将以可变速率被输出。 当将数据从串行总线加载到锁存器中时，刷新时，当前数据被加载到锁存器的所有N个单元中，每个随后的时钟加载少一个锁存器。 当并行总线上的单元的内容被忽略时，该单元与前一个单元同时关闭，以便留下冗余数据。

公开(公告)号：US20140317345A1

公开(公告)日：2014-10-23

申请号：US13865823

申请日：2013-04-18

Applicant: XEROX CORPORATION

Inventor： XING LI

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G06F3/0605 ,  G06F3/067 ,  G06F12/0292 ,  H03M7/30 ,  H03M7/3088 ,  H03M7/6011 ,  H03M7/6017

Abstract: A method, computer readable medium, and apparatus for implementing a compression are disclosed. For example, the method receives a first portion of an input data at a first register, determines a first address based upon the first portion of the input data, reads the first address in a memory to determine if a value stored in the first address is zero, stores a code for the first address of the memory in the first register if the value of the first address is zero, receives a second portion of the input data at a second register, determines a second address based upon the second portion of the input data in the memory, obtains the code from the first register if the second address and the first address are the same and writes the code from the first register in the first address of the memory.

Abstract translation: 公开了一种用于实现压缩的方法，计算机可读介质和装置。 例如，该方法在第一寄存器处接收输入数据的第一部分，基于输入数据的第一部分确定第一地址，读取存储器中的第一地址，以确定存储在第一地址中的值是否为 如果第一地址的值为零，则存储第一寄存器中存储器的第一地址的代码，在第二寄存器处接收输入数据的第二部分，基于第二地址的第二部分确定第二地址 如果第二地址和第一地址相同，则从存储器中输入数据，从第一寄存器获得代码，并将来自第一寄存器的代码写入存储器的第一地址。

公开(公告)号：US20140281101A1

公开(公告)日：2014-09-18

申请号：US14288153

申请日：2014-05-27

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep ROHILLA

IPC: G06F13/28

CPC classification number: G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract translation: 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US20140225110A1

公开(公告)日：2014-08-14

申请号：US13765208

申请日：2013-02-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gopalkrishna Ullal Nayak ,  Matthew Craig Bullock

IPC: H01L21/66

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C29/04 ,  H01L22/14 ,  H01L22/20

Abstract: In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.

Abstract translation: 在用于电子设备的半导体芯片中，可编程修剪代码与默认修剪代码无关。 通过选择默认修剪代码或可编程修剪代码来生成输出修剪代码。 通过在至少一个半导体芯片的制造期间通过在金属互连层中根据第一金属布局形成金属互连来设定多个半导体芯片的默认修剪代码。 通过在后续半导体芯片的制造期间通过在金属互连层中根据第二金属布局形成金属互连来复位默认修剪代码。