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公开(公告)号:US20170219744A1
公开(公告)日:2017-08-03
申请号:US15409623
申请日:2017-01-19
Applicant: Seiko Epson Corporation
Inventor: Toru Nimura
IPC: G02B3/00 , G02B27/14 , G03B21/00 , G02F1/1335 , G02F1/1343 , G02B5/30 , G02F1/1368
CPC classification number: G02B3/0025 , G02B3/0056 , G02B3/0068 , G02B5/3083 , G02B27/149 , G02F1/133526 , G02F1/134309 , G02F1/13439 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G03B21/006 , H04N9/3105
Abstract: An element substrate is formed as a lens array substrate on which a plurality of lenses are formed. In a method of manufacturing the lens array substrate, first recess sections are formed on one surface of the substrate, and then a plurality of lens surfaces, which include concave surfaces, are formed at the bottoms of the first recess sections 195. Subsequently, after a light-transmitting lens layer is formed to fill the inside of the first recess sections, flattening is performed while the lens layer is removed. Here, the surface of the lens layer on a side opposite to the substrate is a planar surface which is contiguous to an outside area that is positioned on the outer side of the first recess sections on the one surface of the substrate.
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公开(公告)号:US20170212625A1
公开(公告)日:2017-07-27
申请号:US15413607
申请日:2017-01-24
Applicant: Samsung Display Co., Ltd
Inventor: Jongwon LEE , Jongoh KIM , Jeong-Young KIM , Sooguy RHO , Juyong PARK
IPC: G06F3/041 , G02F1/1343 , G02F1/1333
CPC classification number: G06F3/0412 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/13439 , G02F1/1368 , G02F2001/133519 , G02F2201/121 , G02F2201/123 , G02F2203/01 , G06F3/044 , G06F2203/04103
Abstract: A touch display apparatus includes a first substrate, a touch electrode, an insulating pattern, a second substrate and a liquid crystal layer. The touch electrode is disposed on a first surface of the first substrate. The insulating pattern is disposed on the touch electrode. The insulating pattern has a refractive index same as a refractive index of the touch electrode. The second substrate faces a second surface of the first substrate opposite to the first surface of the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.
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公开(公告)号:US20170212396A1
公开(公告)日:2017-07-27
申请号:US15075151
申请日:2016-04-05
Inventor: Shangcao CAO
IPC: G02F1/1362 , G02F1/1368 , G02F1/1343 , G02F1/1333 , G02F1/1335
CPC classification number: G02F1/136213 , G02F1/133345 , G02F1/133514 , G02F1/134309 , G02F1/134363 , G02F1/136286 , G02F1/1368 , G02F2001/133397 , G02F2201/121 , G02F2201/123 , G02F2202/104
Abstract: An array substrate, a liquid crystal display panel and a liquid crystal display device of the present disclosure provided are designed to form a MIS storage capacitor by the polycrystalline semiconductor layer, the first metal layer and the insulating layer between the two or the polycrystalline semiconductor layer, the second metal layer and the insulating layer between the two. When one side of the first metal layer or the second metal layer is receiving the negative gray scale voltage, a P—Si in the polycrystalline semiconductor layer will gather to form a cavity, when receiving the positive gray scale voltage, a blocking layer will be formed on the P—Si to reduce the capacity of the MIS storage capacitor.
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公开(公告)号:US20170210985A1
公开(公告)日:2017-07-27
申请号:US15329422
申请日:2015-07-23
Applicant: DIC Corporation
Inventor: Shinji OGAWA , Yoshinori IWASHITA
IPC: C09K19/30 , G02F1/1337 , G02F1/1343 , G02F1/1368 , G02F1/1362
CPC classification number: C09K19/3003 , C09K19/02 , C09K19/12 , C09K19/30 , C09K19/44 , C09K2019/123 , C09K2019/3004 , C09K2019/3009 , C09K2019/301 , C09K2019/3016 , C09K2019/3027 , G02F1/1337 , G02F1/134309 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F2001/133738 , G02F2001/134372 , G02F2201/121 , G02F2201/123
Abstract: The present invention provides a liquid crystal display element that exhibits a large potential-difference gradient due to inter-electrode distance in FFS mode or the like and contains one or more compounds selected from the group of compounds represented by General Formula (I) and one or more compounds selected from the group of compounds represented by General Formula (II). The liquid crystal display element of the present invention provides a liquid crystal display element which uses a liquid crystal composition with negative dielectric anisotropy and makes it possible to realize excellent display characteristics such as flicker when used in a liquid crystal display element that exhibits a large potential-difference gradient due to inter-electrode distance in FFS mode or the like, without deteriorating the burn-in characteristics of the display element or various liquid crystal-display-element characteristics such as dielectric anisotropy, viscosity, maximum nematic-phase temperature, nematic-phase stability at low temperatures, or γ1.
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公开(公告)号:US20170205951A1
公开(公告)日:2017-07-20
申请号:US15479364
申请日:2017-04-05
Applicant: Japan Display Inc.
Inventor: Shuuichirou MATSUMOTO
IPC: G06F3/041 , G02F1/1368 , G02F1/1343 , G02F1/1345 , G02F1/1333 , G06F3/044 , G02F1/1362
CPC classification number: G06F3/0416 , G02F1/13338 , G02F1/134336 , G02F1/13439 , G02F1/13452 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , G02F2201/121 , G02F2201/123 , G06F3/0412 , G06F3/044 , G06F2203/04102 , G06F2203/04103
Abstract: In a liquid crystal display device, a second substrate includes a detection electrode of a touch panel, pixels include pixel electrodes and counter electrodes, the counter electrodes are divided into a plurality of blocks, the counter electrodes of the divided blocks are provided in common to the pixels on a plurality of display lines being side by side, the counter electrodes of the divided blocks are used as scanning electrodes of the touch panel as well, the liquid crystal display device includes a semiconductor chip configured to supply a counter voltage and a touch panel scanning voltage to the counter electrodes of the divided blocks, the semiconductor chip includes a first terminal group formed on a side of a display area side configured by the plurality of pixels.
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公开(公告)号:US20170200425A1
公开(公告)日:2017-07-13
申请号:US14416373
申请日:2014-10-22
Inventor: Huan LIU
IPC: G09G3/36 , G02F1/1362
CPC classification number: G09G3/3614 , G02F1/136286 , G02F2201/121 , G09G3/36 , G09G3/3648 , G09G2300/0426 , G09G2310/08 , G09G2320/0209 , G09G2320/0214
Abstract: A liquid crystal display panel and a liquid crystal display comprising the same are disclosed. The liquid crystal display panel comprise: a plurality of pixels configured in an array, which is formed by a plurality of data lines and a plurality of scan lines that arc arranged perpendicularly with respect to the plurality of data lines. The plurality of scan lines comprise: at least two scan lines arranged in correspondence with each line of pixels, the at least two scan lines being alternately connected to each successive pixel located in a corresponding line, wherein each line of pixels is scanned in a plurality of individual time periods. During each time period, when pixel drive signals are input into pixels connected to one of the at least two scan lines via corresponding data lines, the sum of the variation of the pixel drive signals and the variation of input signals of data lines corresponding to pixels connected to the rest of the at least two scan lines equals 0, so that a common electrode voltage will not deviate from a pre-determined voltage. As a result, the phenomenon of deviation generated due to couplings of the common-electrode voltage to data lines can be largely relieved, thus eliminating the phenomenon of horizontal crosstalk caused thereby in the prior art.
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公开(公告)号:US20170199407A1
公开(公告)日:2017-07-13
申请号:US14901250
申请日:2015-11-27
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor: Zuyou YANG
IPC: G02F1/1333 , G02F1/1368 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/13338 , G02F1/133345 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/1368 , G02F2001/133357 , G02F2001/134318 , G02F2001/134381 , G02F2001/136231 , G02F2001/13685 , G02F2201/121 , G02F2202/104 , G06F3/0412 , H01L27/12 , H01L27/1248 , H01L29/78633 , H01L29/78675
Abstract: An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.
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公开(公告)号:US09704884B2
公开(公告)日:2017-07-11
申请号:US14436063
申请日:2015-01-21
Inventor: Tianming Dai
IPC: H01L27/12 , G02F1/1343 , G02F1/1368 , H01L21/311 , H01L21/027 , H01L21/3213 , H01L21/02 , G02F1/1335 , H01L29/786 , H01L21/77 , G02F1/1362
CPC classification number: H01L27/1222 , G02F1/133512 , G02F1/134309 , G02F1/13439 , G02F1/136227 , G02F1/1368 , G02F2001/134318 , G02F2001/136231 , G02F2001/13625 , G02F2001/136295 , G02F2201/121 , G02F2202/104 , H01L21/02532 , H01L21/02595 , H01L21/0273 , H01L21/31116 , H01L21/32133 , H01L21/77 , H01L27/12 , H01L27/1288 , H01L29/78633 , H01L29/78675
Abstract: An array substrate comprises a substrate, a common electrode formed on the substrate, a light shielding layer disposed on the common electrode, an insulating layer disposed on the light shielding layer and the common electrode, a poly-silicon layer, a gate insulating layer, a gate connected with the common electrode by a hole, a medium layer and a source drain. A method for manufacturing the array substrate comprises forming a transparent conductive layer and a first metallic layer on the substrate, forming patterned common electrode and light shielding layer by multiple steps of etching so that a process of photomask can be saved, and forming holes connecting with the common electrode and the gate by a photomask etching process, then manufacturing a medium layer and a source drain. The method adopts seven processes of photomask so that the process is simplified, and the cost is lowered.
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公开(公告)号:US20170192315A1
公开(公告)日:2017-07-06
申请号:US15245544
申请日:2016-08-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Jeongki KIM , Hongbeom LEE , Junyoung JUNG
IPC: G02F1/1343
CPC classification number: G02F1/134309 , G02F1/133707 , G02F2001/133742 , G02F2001/133757 , G02F2001/134345 , G02F2201/121 , G02F2201/122 , G02F2201/123
Abstract: A display substrate includes a base substrate including pixel areas in a first direction and a pixel electrode. The pixel electrode includes a sub-pixel electrode including first and second unit electrodes connected by a first connector, and a first slit non-parallel to the first direction between the first and second unit electrodes. The first unit electrode includes a first vertical stem portion at a side of the pixel area, and a first horizontal stem portion including an end connected to the first vertical stem portion and an end adjacent to a first vertical stem portion of an adjacent pixel electrode. The second unit electrode includes a second vertical stem portion at another side of the pixel area, and a second horizontal stem portion including an end connected to the second vertical stem portion and another end adjacent to a second vertical stem portion of another adjacent pixel electrode.
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公开(公告)号:US20170192311A1
公开(公告)日:2017-07-06
申请号:US14787766
申请日:2015-10-13
Inventor: Qiming Gan
IPC: G02F1/1343 , G02F1/1362 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/134309 , G02F1/133345 , G02F1/133707 , G02F1/136227 , G02F1/1368 , G02F2001/133742 , G02F2001/136236 , G02F2001/13775 , G02F2201/121 , G02F2201/122 , G02F2201/123 , G02F2203/01 , H01L27/1248
Abstract: The present invention provides a PSVA liquid crystal display panel, comprising an upper substrate (1), a lower substrate (2) oppositely located to the upper substrate (1) and a liquid crystal layer (3) located between the upper substrate (1) and the lower substrate (2); the lower substrate (2) comprises a second substrate (21), a thin film transistor, a passivation layer (22) and a pixel electrode (23); the lower substrate (2) comprises a plurality of pixel areas, and the passivation layer (22) is a passivation layer which is patterned, and is respectively formed the same pattern corresponding to the plurality of pixel areas, and the pattern comprises a plurality of trenches (221) extending toward various directions; the pixel electrode (23) is entirely attached to the passivation layer (22) which is patterned and comprises a corresponding pattern with the passivation layer (22); a depth of the trench (221) is 2000-4000 Å. The PSVA liquid crystal display panel of the present invention possesses higher transmittance and excellent optical performance.
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