公开(公告)号：US20230009329A1

公开(公告)日：2023-01-12

申请号：US17850207

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

公开(公告)号：US20230008833A1

公开(公告)日：2023-01-12

申请号：US17849903

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US11550348B2

公开(公告)日：2023-01-10

申请号：US17211545

申请日：2021-03-24

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Gourav Garg

IPC: G05F1/56 ,  G01R31/28 ,  H03K19/20

Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.

公开(公告)号：US20230006679A1

公开(公告)日：2023-01-05

申请号：US17931043

申请日：2022-09-09

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Prashutosh GUPTA ,  Ankit GUPTA

IPC: H03L7/081 ,  H03L7/085

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

公开(公告)号：US11522446B2

公开(公告)日：2022-12-06

申请号：US17494244

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  G05F1/59 ,  H02M1/00

Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

公开(公告)号：US20220359714A1

公开(公告)日：2022-11-10

申请号：US17736767

申请日：2022-05-04

Applicant: Exagan SAS ,  STMicroelectronics International N.V.

Inventor： Matthieu NONGAILLARD ,  Thomas OHEIX

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L25/07

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

公开(公告)号：US20220359435A1

公开(公告)日：2022-11-10

申请号：US17733589

申请日：2022-04-29

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Stephane MONFRAY ,  Siddhartha DHAR ,  Alain FLEURY

IPC: H01L23/66 ,  H01L23/373 ,  H01L23/42 ,  H01L21/48

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

公开(公告)号：US11475960B2

公开(公告)日：2022-10-18

申请号：US17306266

申请日：2021-05-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Fabio Enrico Carlo Disegni ,  Laura Capecchi ,  Marcella Carissimi ,  Vikas Rana ,  Cesare Torti

IPC: G11C13/00 ,  G11C16/10 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C16/32

Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

公开(公告)号：US11463098B2

公开(公告)日：2022-10-04

申请号：US17342416

申请日：2021-06-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur Bal ,  Sri Ram Gupta ,  Rupesh Singh

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

公开(公告)号：US11444580B2

公开(公告)日：2022-09-13

申请号：US16837783

申请日：2020-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Riju Biswas

IPC: H03F3/45 ,  H03F1/26 ,  H03F3/68

Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.