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181.发明申请公开(公告)号：US20180351592A1
公开(公告)日：2018-12-06
申请号：US15609337
申请日：2017-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban
IPC: H04B1/10 , H04B17/318 , H04B17/336 , H03F3/195 , H03G3/00
CPC classification number: H04B1/1036 , H03F3/195 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2200/465 , H03G3/3068 , H03G3/3078
Abstract: In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.
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公开(公告)号：US20180348295A1
公开(公告)日：2018-12-06
申请号：US15609996
申请日：2017-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Ernest T. Stroud , Stefan N. Mastovich , Huanhui Zhan , Tamás Marozsák , András V. Horváth
IPC: G01R31/28
Abstract: An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.
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公开(公告)号：US10141971B1
公开(公告)日：2018-11-27
申请号：US15815920
申请日：2017-11-17
Applicant: Silicon Laboratories Inc.
Inventor： Mohamed Elkholy , Ayman Shafik , Yang Gao , Arup Mukherji , Navin Harwalkar
Abstract: Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.
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公开(公告)号：US20180321875A1
公开(公告)日：2018-11-08
申请号：US15589217
申请日：2017-05-08
Applicant: Silicon Laboratories Inc.
Inventor： Thomas S. David
CPC classification number: G06F11/1076 , G06F11/2215 , G06F12/1425 , G06F2212/1056
Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.
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公开(公告)号：US10110177B1
公开(公告)日：2018-10-23
申请号：US15662375
申请日：2017-07-28
Applicant: Silicon Laboratories Inc.
Inventor： Mustafa Koroglu
Abstract: In one aspect, an apparatus includes: a first power amplifier to receive a first voltage signal and to output a first current; a second power amplifier to receive a second voltage signal and to output a second current; and a transformer coupled to the first power amplifier and the second power amplifier. The transformer may have multiple differential input ports to realize a controllable impedance based on a desired output power level.
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Patent Agency Ranking
公开(公告)号：US10084376B2
公开(公告)日：2018-09-25
申请号：US13917387
申请日：2013-06-13
Applicant: Silicon Laboratories Inc.
Inventor： Sean A. Lofthouse
CPC classification number: H02M3/155 , H02M2001/0045 , H02M2001/009 , Y10T307/406
Abstract: A circuit such as a subscriber line interface circuit (SLIC) has a multiple output power converter including an inductive converter, a first passive rectifier, a first capacitor, and a second passive rectifier. The inductive converter has a voltage input terminal for receiving an input voltage, and a voltage output terminal. The first passive rectifier has an input coupled to the voltage output terminal of the inductive power converter, and an output for providing a first power supply voltage. The first capacitor has a first terminal coupled to the output terminal of the inductive converter, and a second terminal. The second passive rectifier has an input coupled to the second terminal of the first capacitor, and an output terminal for providing a second power supply voltage different from the first power supply voltage.
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公开(公告)号：US20180269877A1
公开(公告)日：2018-09-20
申请号：US15459226
申请日：2017-03-15
Applicant: Silicon Laboratories Inc.
Inventor： Ernest T. Stroud , Stefan N. Mastovich
CPC classification number: H03K19/018507 , H01L27/0251 , H01L27/0266 , H02M3/07 , H03K3/011 , H03K5/08 , H03K5/24
Abstract: An integrated circuit includes an input terminal configured to receive an input signal, a reference voltage node configured to provide a control voltage, and a pass transistor comprising a first terminal coupled to a first node, a control terminal coupled to the reference voltage node, and a second terminal coupled to the input terminal. The control voltage has a control voltage level sufficient to allow a signal to pass from the second terminal to the first terminal. The pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of the input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signal to the first node in response to the voltage level being above the first voltage level. At most, a negligible DC current flows through the input terminal into the second terminal.
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公开(公告)号：US10067478B1
公开(公告)日：2018-09-04
申请号：US15837472
申请日：2017-12-11
Applicant: Silicon Laboratories Inc.
Inventor： Raghunandan Kolar Ranganathan
IPC: G04F10/00 , H03K3/033 , H03K5/1534 , H03K5/159
Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.
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公开(公告)号：US10057051B2
公开(公告)日：2018-08-21
申请号：US14983830
申请日：2015-12-30
Applicant: Silicon Laboratories Inc.
Inventor： Yunteng Huang
CPC classification number: H04L7/0332 , H03L7/0805 , H03L7/081 , H03L7/085 , H03L7/093 , H03L7/0991 , H03L7/0994 , H04J3/0661 , H04L7/002 , H04L27/2272
Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.
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公开(公告)号：US10041981B2
公开(公告)日：2018-08-07
申请号：US14927959
申请日：2015-10-30
Applicant: Silicon Laboratories Inc.
Inventor： Xiaodong Wang
Abstract: A capacitor sense system includes a pad for coupling to an external capacitor. A current digital to analog converter (DAC) supplies current to charge the external capacitor. A reference capacitor is charged by a current source. A first comparator compares a voltage across the external capacitor sensed at the pad to a reference voltage and generates a first comparison. A second comparator compares a voltage across a reference capacitor to the reference voltage and generates a second comparison. The stored first and second comparisons are used to control the current DAC. First and second AC coupling capacitors are coupled respectively between the pad and the first comparator and between the reference capacitor and the second comparator. Sensing at the pad allows more accuracy and the AC coupling capacitors provide better matching and allow for different DC biases to be set for the external capacitor and the first comparator.
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