公开(公告)号：US20130037886A1

公开(公告)日：2013-02-14

申请号：US13206533

申请日：2011-08-10

Applicant: Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC: H01L27/092 ,  H01L21/782 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

公开(公告)号：US20130009288A1

公开(公告)日：2013-01-10

申请号：US13177573

申请日：2011-07-07

Applicant: Shu-Hui Hu ,  Shih-Feng Su ,  Hui-Shen Shih ,  Chih-Chien Liu ,  Po-Chun Chen ,  Ya-Jyuan Hung ,  Bin-Siang Tsai ,  Chin-Fu Lin

Inventor： Shu-Hui Hu ,  Shih-Feng Su ,  Hui-Shen Shih ,  Chih-Chien Liu ,  Po-Chun Chen ,  Ya-Jyuan Hung ,  Bin-Siang Tsai ,  Chin-Fu Lin

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L21/76801

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括以下步骤：提供衬底; 在所述衬底上形成电介质层，其中所述电介质层包括金属互连; 在所述电介质层上形成顶部金属层; 并通过高密度等离子体化学气相沉积（HDPCVD）工艺在顶层金属层上形成钝化层。

公开(公告)号：US20120068288A1

公开(公告)日：2012-03-22

申请号：US12961521

申请日：2010-12-07

Applicant: Chung-Hsien Hsin ,  Hsiu-Wen Tu ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

Inventor： Chung-Hsien Hsin ,  Hsiu-Wen Tu ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L21/56

CPC classification number: H01L27/14683 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A manufacturing method of a molded image sensor packaging structure with a predetermined focal length and the structure using the same are disclosed. The manufacturing method includes: providing a substrate; providing a sensor chip disposed on the substrate; providing a lens module set over the sensing area of the chip to form a semi-finished component; providing a mold that has an upper mold member with a buffer layer; disposing the semi-finished component into the mold to form a mold cavity therebetween; injecting a molding compound into the mold cavity; and after transfer molding the molding compound, opening the mold and performing a post mold cure process to cure the molding compound. The buffer layer can fill the air gap between the upper surface of the lens module and the upper mold member, thereby preventing the upper surface of the lens module from being polluted by the molding compound.

Abstract translation: 公开了一种具有预定焦距的模制图像传感器封装结构的制造方法及其结构。 该制造方法包括：提供基板; 提供设置在所述基板上的传感器芯片; 提供在芯片的感测区域上设置的透镜模块以形成半成品组件; 提供具有带有缓冲层的上模构件的模具; 将半成品配置到模具中以在其间形成模腔; 将模塑料注射到模腔中; 并且在转移成型模塑料之后，打开模具并执行后模固化工艺以固化模塑料。 缓冲层可以填充透镜模块的上表面和上模具构件之间的气隙，从而防止透镜模块的上表面被模塑料污染。

公开(公告)号：US20110254060A1

公开(公告)日：2011-10-20

申请号：US12760782

申请日：2010-04-15

Applicant: Yu-Ru YANG ,  Tzung-Ying Lee ,  Chin-Fu Lin ,  Chi-Mao Hsu

Inventor： Yu-Ru YANG ,  Tzung-Ying Lee ,  Chin-Fu Lin ,  Chi-Mao Hsu

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/518 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a metal gate structure is provided. Firstly, a high-K gate dielectric layer is formed on a semiconductor substrate. Then, a first metal-containing layer having a surface away from the gate dielectric layer is formed on the gate dielectric layer. After that, the surface of the first metal-containing layer is treated to improve the nitrogen content thereof of the surface. Subsequently, a silicon layer is formed on the first metal-containing layer. Because the silicon layer is formed on the surface having high nitrogen content, the catalyzing effect to the silicon layer resulted from the metal material in the first metal-containing layer can be prevented. As a result, the process yield is improved.

Abstract translation: 提供一种制造金属栅极结构的方法。 首先，在半导体衬底上形成高K栅介质层。 然后，在栅极电介质层上形成具有离开栅极电介质层的表面的第一含金属层。 之后，处理第一含金属层的表面以改善其表面的氮含量。 随后，在第一含金属层上形成硅层。 由于在具有高氮含量的表面上形成硅层，所以可以防止由第一含金属层中的金属材料产生的对硅层的催化作用。 结果，工艺产量提高。

公开(公告)号：US08034690B2

公开(公告)日：2011-10-11

申请号：US12696055

申请日：2010-01-29

Applicant: Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

Inventor： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

IPC: H01L21/336

CPC classification number: H01L21/311

Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Abstract translation: 提供蚀刻氧化物层和氮化物层的示例性方法。 特别地，提供了基板。 基板的表面具有从其突出的隔离结构。 第一氧化物层，氮化物层和第二氧化物层依次设置在衬底的表面上，其中第一氧化物层未被覆盖在隔离结构上，氮化物层形成在第一氧化物层上，第二氧化物 层叠在氮化物层上。 通过使用非掩蔽隔离结构的蚀刻掩模进行各向同性蚀刻处理，从而去除第二氧化物层的未掩模部分和氮化物层的未掩模部分，并进一步暴露隔离结构的侧壁。 由于过蚀刻，第一氧化物层的未掩模部分通常被部分去除。

公开(公告)号：US20110189859A1

公开(公告)日：2011-08-04

申请号：US12696055

申请日：2010-01-29

Applicant: Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

Inventor： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

IPC: H01L21/311

CPC classification number: H01L21/311

Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Abstract translation: 提供蚀刻氧化物层和氮化物层的示例性方法。 特别地，提供了基板。 基板的表面具有从其突出的隔离结构。 第一氧化物层，氮化物层和第二氧化物层依次设置在衬底的表面上，其中第一氧化物层未被覆盖在隔离结构上，氮化物层形成在第一氧化物层上，第二氧化物 层叠在氮化物层上。 通过使用非掩蔽隔离结构的蚀刻掩模进行各向同性蚀刻处理，从而去除第二氧化物层的未掩模部分和氮化物层的未掩模部分，并进一步暴露隔离结构的侧壁。 由于过蚀刻，第一氧化物层的未掩模部分通常被部分去除。

公开(公告)号：US20110127589A1

公开(公告)日：2011-06-02

申请号：US12629064

申请日：2009-12-02

Applicant: Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract translation: 一种形成具有金属栅极的半导体结构的方法。 首先，提供半导体衬底。 随后，至少在半导体衬底上形成栅极结构。 之后，形成围绕栅结构的间隔结构。 然后，形成层间电介质。 之后，对层间电介质进行平面化处理。 然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。 暴露于开口的间隔结构的部分被去除以扩大开口。 之后，通过开口完全除去牺牲层。 最后，形成栅极导电层以填充开口。

公开(公告)号：US07538024B2

公开(公告)日：2009-05-26

申请号：US10908229

申请日：2005-05-03

Applicant: Hsien-Che Teng ,  Chin-Fu Lin ,  Meng-Chi Chen

Inventor： Hsien-Che Teng ,  Chin-Fu Lin ,  Meng-Chi Chen

IPC: H01L21/4763

CPC classification number: H01L21/2855 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873

Abstract: A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially performed to form a substrate-protecting layer and a tantalum nitride layer in the dual-damascene hole. And then a copper layer is formed in the dual-damascene hole.

Abstract translation: 一种用于制造双镶嵌铜结构的方法包括提供其上具有电介质层的半导体衬底和位于电介质层中的双镶嵌孔，其中半导体衬底的一部分暴露在双镶嵌孔中。 依次进行PVD工艺和原子CVD工艺以在双镶嵌孔中形成衬底保护层和氮化钽层。 然后在双镶嵌孔中形成铜层。

公开(公告)号：US09559189B2

公开(公告)日：2017-01-31

申请号：US13447286

申请日：2012-04-16

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Abstract translation: 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供了一种制造非平面FET的方法。

公开(公告)号：US09166020B2

公开(公告)日：2015-10-20

申请号：US13037383

申请日：2011-03-01

Applicant: Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

Inventor： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract translation: 一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理 原位。