公开(公告)号：US20140042599A1

公开(公告)日：2014-02-13

申请号：US13584015

申请日：2012-08-13

Applicant: Chung-Lin Wu ,  Steven Sapp ,  Bigildis Dosdos ,  Suresh Belani ,  Sunggeun Yoon

Inventor： Chung-Lin Wu ,  Steven Sapp ,  Bigildis Dosdos ,  Suresh Belani ,  Sunggeun Yoon

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/4334 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/7813 ,  H01L29/7828 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.

Abstract translation: 多芯片无引线模块200具有集成电路（IC）150，双重信道mosfet 110，IC引线210,211,212，栅极引线213,213和封装在树脂250中的源极引线217-220。IC 150 并且双n沟道MOSFET 110面朝下安装在引线上。 IC引线210,211,212由平面金属制成，并且使用倒装芯片技术分别连接到IC 150上的电极TEST，VDD和VM，以将铜柱或铜螺柱上的引线组装。

公开(公告)号：US20130132640A1

公开(公告)日：2013-05-23

申请号：US13366271

申请日：2012-02-04

Applicant: Chung-Lin Wu ,  Yi-Hsiang Huang

Inventor： Chung-Lin Wu ,  Yi-Hsiang Huang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7205

Abstract: A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法，以及存储器控制器和使用其的存储器存储装置。 该方法包括将可重写非易失性存储器模块的物理块划分为数据区和备用区并配置逻辑块。 该方法还包括从备用区选择物理块作为对应于逻辑块的备用物理块，并且仅使用备用物理块的较低物理页来存储要写入逻辑块的更新数据。 该方法还包括将逻辑块的所有逻辑页的有效数据移动到数据区的物理块中，其中在物理块中与之对应的每个下部物理页和上部物理页一起编程。 因此，该方法可以有效地提高写入数据的速度和可靠性。

公开(公告)号：US08278742B2

公开(公告)日：2012-10-02

申请号：US13019488

申请日：2011-02-02

Applicant: Chung-Lin Wu ,  Rajeev D. Joshi

Inventor： Chung-Lin Wu ,  Rajeev D. Joshi

IPC: H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/28

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/4334 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract translation: 半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。 环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。 壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。 支撑臂相对于平面环形基座11的内表面16以钝角设置。

公开(公告)号：US20110230046A1

公开(公告)日：2011-09-22

申请号：US13151495

申请日：2011-06-02

Applicant: Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

Inventor： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

IPC: H01L21/28

CPC classification number: H01L23/49513 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099

Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

Abstract translation: 公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。 沟槽减小了掺入骰子的器件的导通电阻。 弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。 还公开了使用骰子的包裹以及制造骰子的方法。

公开(公告)号：US20110066818A1

公开(公告)日：2011-03-17

申请号：US12822385

申请日：2010-06-24

Applicant: Hsiang-Hsiung Yu ,  Chung-Lin Wu ,  Yi-Hsiang Huang ,  Yu-Chung Shen

Inventor： Hsiang-Hsiung Yu ,  Chung-Lin Wu ,  Yi-Hsiang Huang ,  Yu-Chung Shen

IPC: G06F12/14 ,  G06F12/00 ,  G06F12/16

CPC classification number: G06F21/10 ,  G06F21/78

Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.

Abstract translation: 提供存储装置，存储器控制器和数据保护方法。 该方法包括当接收到主机发送的读取命令时，采用相应的输出流量限制，以根据包括在读取命令中的位置信息或类型的类型来确定对主机对应于读取命令的读取数据执行的操作 主机和存储设备之间的传输接口。 该方法还包括执行存储设备的干扰过程，以防止读取数据被复制到主机，或者当识别操作是复制操作时，将读取的数据复制到主机的速度降低。

公开(公告)号：US20100117231A1

公开(公告)日：2010-05-13

申请号：US12690179

申请日：2010-01-20

Applicant: Dennis Lang ,  Sonbol Vaziri ,  James Kent Naylor ,  Eric Woolsey ,  Chung-Lin Wu ,  Mike Gruenhagen ,  Neill Thornton

Inventor： Dennis Lang ,  Sonbol Vaziri ,  James Kent Naylor ,  Eric Woolsey ,  Chung-Lin Wu ,  Mike Gruenhagen ,  Neill Thornton

IPC: H01L23/498

CPC classification number: H01L23/3114 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.

Abstract translation: 晶片级芯片级封装（WLCSP）包括具有多个焊料凸块焊盘的半导体器件，每个焊料凸块焊盘上方的图案化钝化区域，每个焊料凸块焊盘上的图案化凸点下金属化（UBM）区域，以及 钝化区域，UBM区域的一部分上的聚酰亚胺区域和钝化区域，形成在每个UBM区域上的焊料凸块。

公开(公告)号：US20090166850A1

公开(公告)日：2009-07-02

申请号：US11968602

申请日：2008-01-02

Applicant: Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

Inventor： Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

IPC: H01L21/50 ,  H01L23/40

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/40 ,  H01L23/49562 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Abstract translation: 本发明的示例性半导体管芯封装具有设置在半导体管芯的第一表面和散热部件之间的金属氧化物衬底，其具有导电裸片夹或设置在金属氧化物衬底和金属氧化物衬底之间的一个或多个电互连迹线 半导体芯片的第一表面。 散热部件可以包括散热器或适配器板，散热器可以耦合到适配器板。 导电芯片夹或电迹线为半导体管芯的第一表面提供电连接，同时金属氧化物衬底将电芯与散热部件绝缘，并提供高导热性的路径 在模具和散热部件之间。 半导体管芯的第二表面可以自由地连接到电路板，或者可以将引线框架或互连衬底附接到其上。

公开(公告)号：US20090072362A1

公开(公告)日：2009-03-19

申请号：US12170523

申请日：2008-07-10

Applicant: Chung-Lin Wu ,  Rajeev D. Joshi

Inventor： Chung-Lin Wu ,  Rajeev D. Joshi

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/4334 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract translation: 半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。 环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。 壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。 支撑臂相对于平面环形基座11的内表面16以钝角设置。

公开(公告)号：US07468548B2

公开(公告)日：2008-12-23

申请号：US11299270

申请日：2005-12-09

Applicant: Chung-Lin Wu ,  Rajeev D. Joshi

Inventor： Chung-Lin Wu ,  Rajeev D. Joshi

IPC: H01L23/495

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/4334 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract translation: 半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。 环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。 壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。 支撑臂相对于平面环形基座11的内表面16以钝角设置。

公开(公告)号：US20080054461A1

公开(公告)日：2008-03-06

申请号：US11847512

申请日：2007-08-30

Applicant: Dennis Lang ,  Sonbol Vaziri ,  James Naylor ,  Eric Woolsey ,  Chung-Lin Wu ,  Mike Gruenhagen ,  Neill Thornton

Inventor： Dennis Lang ,  Sonbol Vaziri ,  James Naylor ,  Eric Woolsey ,  Chung-Lin Wu ,  Mike Gruenhagen ,  Neill Thornton

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.

Abstract translation: 晶片级芯片级封装（WLCSP）包括具有多个焊料凸块焊盘的封装半导体器件，每个焊料凸块焊盘上方的图案化钝化区域，每个焊料凸块焊盘上的图案化凸块下金属化（UBM）区域，以及 钝化区域，UBM区域和钝化区域的一部分上的聚酰亚胺区域，形成在每个UBM区域上的焊料凸块以及围绕半导体管芯的封装材料，除了每个焊料凸块的至少一部分之外。