公开(公告)号：US20090170221A1

公开(公告)日：2009-07-02

申请号：US11965972

申请日：2007-12-28

Applicant: Jeannette Michelle Jacques ,  Deepak A. Ramappa

Inventor： Jeannette Michelle Jacques ,  Deepak A. Ramappa

IPC: H01L21/66

CPC classification number: H01L21/76808 ,  H01L21/02063 ,  H01L21/76814

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Abstract translation: 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。

公开(公告)号：US08728951B2

公开(公告)日：2014-05-20

申请号：US13563056

申请日：2012-07-31

Applicant: Ludovic Godet ,  Xianfeng Lu ,  Deepak A. Ramappa

Inventor： Ludovic Godet ,  Xianfeng Lu ,  Deepak A. Ramappa

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01J37/32366 ,  C23C16/04 ,  C23C16/50 ,  H01J37/3056 ,  H01J37/3178 ,  H01J2237/08 ,  H01J2237/31732

Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.

Abstract translation: 一种处理衬底的方法包括执行第一曝光，其包括在等离子体室中产生含有反应气体离子的等离子体，并在衬底和等离子体室之间产生偏置电压。 该方法还包括提供等离子体护套改性剂，其具有设置在等离子体和衬底之间的孔，并可操作以将反应性气体离子引向衬底，并且在反应性气体离子被引导到等离子体室和衬底区域之间建立压力差 底物。

公开(公告)号：US20110151610A1

公开(公告)日：2011-06-23

申请号：US12646407

申请日：2009-12-23

Applicant: Deepak A. RAMAPPA ,  Ludovic Godet

Inventor： Deepak A. RAMAPPA ,  Ludovic Godet

IPC: H01L31/18

CPC classification number: H01L31/068 ,  H01J37/32366 ,  H01J37/32422 ,  H01J37/32623 ,  H01L21/3065 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods to texture or fabricate workpieces are disclosed. The workpiece may be, for example, a solar cell. This texturing may involve etching or localized sputtering using a plasma where a shape of a boundary between the plasma and the plasma sheath is modified with an insulating modifier. The workpiece may be rotated in between etching or sputtering steps to form pyramids. Regions of the workpiece also may be etched or sputtered with ions formed from a plasma adjusted by an insulating modifier and doped. A metal layer may be formed on these doped regions.

Abstract translation: 公开了纹理或制造工件的方法。 工件可以是例如太阳能电池。 这种纹理化可能包括使用等离子体进行蚀刻或局部溅射，其中等离子体和等离子体护套之间的边界的形状用绝缘改性剂改性。 可以在蚀刻或溅射步骤之间旋转工件以形成金字塔。 工件的区域也可以用由通过绝缘改性剂调节的等离子体形成的离子进行蚀刻或溅射并掺杂。 可以在这些掺杂区域上形成金属层。

公开(公告)号：US07910477B2

公开(公告)日：2011-03-22

申请号：US11965972

申请日：2007-12-28

Applicant: Jeannette Michelle Jacques ,  Deepak A. Ramappa

Inventor： Jeannette Michelle Jacques ,  Deepak A. Ramappa

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/02063 ,  H01L21/76814

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Abstract translation: 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。

公开(公告)号：US07312151B2

公开(公告)日：2007-12-25

申请号：US11334181

申请日：2006-01-17

Applicant: Aaron Frank ,  David Gonzalez ,  John DeGenova ,  Srinavas Raghavan ,  Deepak A. Ramappa

Inventor： Aaron Frank ,  David Gonzalez ,  John DeGenova ,  Srinavas Raghavan ,  Deepak A. Ramappa

IPC: H01L21/44

CPC classification number: H01L21/76856 ,  B08B7/0057 ,  C25D5/34 ,  H01L21/321 ,  H01L21/67028 ,  H01L21/67115 ,  H01L21/76862 ,  H01L21/76873

Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

Abstract translation: 本发明提供了一种从已沉积在半导体衬底（206）上的铜籽晶层去除有机污染物（216）的系统。 本发明提供一种将半导体衬底包围的壳体（204）。 紫外线辐射源（210）设置在壳体内。 处理介质（208）也设置在壳体内。 将半导体衬底封装在壳体内并暴露于处理介质。 紫外线辐射源将半​​导体衬底暴露于紫外线辐射，从种子层解吸污染物。

公开(公告)号：US06869873B2

公开(公告)日：2005-03-22

申请号：US10609889

申请日：2003-06-30

Applicant: Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

Inventor： Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/538 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.

Abstract translation: 与形成随后的电介质膜一起原位进行的硅烷钝化工艺将Cu互连结构的暴露的Cu表面转化为硅化铜。 铜硅化物抑制Cu扩散和电迁移，并在与其它导电材料接触的区域中用作阻挡材料。 铜互连结构的整个铜表面可以在覆盖电介质中形成开口以暴露铜表面的一部分之后被硅化或表面硅化的局部部分。

公开(公告)号：US09062367B2

公开(公告)日：2015-06-23

申请号：US13608709

申请日：2012-09-10

Applicant: Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

Inventor： Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

IPC: C23C14/48 ,  C23C14/12 ,  C23C14/04 ,  H01J37/32

CPC classification number: C23C14/048 ,  H01J37/32412

Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.

Abstract translation: 植入绝缘工件的表面以形成疏水或亲水注入区域。 导电涂层沉积在工件上。 在一种情况下，涂层可以是聚合物。 如果这些注入区域是亲水的，则该涂层优选地形成在注入区域上，或者如果注入的区域是疏水的，则优选地形成在非注入区域上。

公开(公告)号：US08716155B2

公开(公告)日：2014-05-06

申请号：US13610322

申请日：2012-09-11

Applicant: Deepak A. Ramappa ,  Kyu-Ha Shim

Inventor： Deepak A. Ramappa ,  Kyu-Ha Shim

IPC: H01L21/469

CPC classification number: H01L21/28282 ,  H01L29/4234 ,  H01L29/513

Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.

Abstract translation: 公开了改善电荷俘获的方法。 一种这样的方法包括在氧化物 - 氮化物 - 氧化物隧道叠层上形成氧化物 - 氮化物 - 氧化物隧道堆叠和氮化硅层。 该氮化硅层被注入离子。 这些离子可以用作电子阱或场。 氮化硅层可以是闪存器件的一部分。

公开(公告)号：US08614143B2

公开(公告)日：2013-12-24

申请号：US12327336

申请日：2008-12-03

Applicant: Makarand R. Kulkarni ,  Deepak A. Ramappa

Inventor： Makarand R. Kulkarni ,  Deepak A. Ramappa

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract translation: 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口暴露的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。

公开(公告)号：US08592230B2

公开(公告)日：2013-11-26

申请号：US13091289

申请日：2011-04-21

Applicant: Deepak A. Ramappa ,  Ludovic Godet

Inventor： Deepak A. Ramappa ,  Ludovic Godet

IPC: H01L21/00

CPC classification number: H01L21/00 ,  C23C14/042 ,  C23C14/48 ,  C23C16/02 ,  C23C16/04 ,  C23C16/50 ,  H01L31/0682 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.

Abstract translation: 图案化衬底的方法包括提供邻近包含等离子体的等离子体室的聚焦板，该聚焦板被配置为通过至少一个孔向等离子体提取离子，所述孔向衬底提供聚焦离子。 该方法还包括将第一离子引导通过至少一个孔到基底的一个或多个第一区域，以便在衬底的一个或多个第一区域上冷凝在衬底环境中提供的第一气态物质。