公开(公告)号：US06349456B1

公开(公告)日：2002-02-26

申请号：US09224338

申请日：1998-12-31

Applicant: Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler ,  Min-Xian Zhang ,  Everett Simons

Inventor： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler ,  Min-Xian Zhang ,  Everett Simons

IPC: H01G700

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

Abstract translation: 一种用于制造具有对准的导电区域和具有期望的处理和尺寸特性的电介质区域的微电子组件的方法。 本发明对于制造集成电容器特别有用，具有通过本发明实现的期望的处理和尺寸特性，为电容器产生可预测的电特性。 该方法通常需要提供具有第一导电层的衬底，在第一导电层上形成电介质层，然后在电介质层上形成第二导电层。 然后去除第二导电层的第一区域以暴露介电层的第一区域，该第一区域又被去除以暴露也被去除的第一导电层的第一区域。 从该工艺中，通过使用上覆层作为掩模，导电和介电层的第一区域各自被去除，使得这些层的剩余的第二区域是共延伸的。

公开(公告)号：US5206820A

公开(公告)日：1993-04-27

申请号：US576304

申请日：1990-08-31

Applicant: Hans H. Ammann ,  Kwokming J. Cheng ,  Richard F. Kovacs ,  Henry B. Micks, Jr. ,  Jamey Potechin ,  Everett Simons ,  Richard C. Steines ,  John G. Tetz

Inventor： Hans H. Ammann ,  Kwokming J. Cheng ,  Richard F. Kovacs ,  Henry B. Micks, Jr. ,  Jamey Potechin ,  Everett Simons ,  Richard C. Steines ,  John G. Tetz

IPC: B23P19/00 ,  B23Q17/24 ,  B23Q41/08 ,  B65G61/00 ,  G05B19/418 ,  G06Q50/00 ,  H01L21/02 ,  H01L21/68 ,  H05K13/08

CPC classification number: H05K13/08 ,  Y02P90/10

Abstract: A metrology system to analyze panel misregistration in a panel manufacturing process includes a software controlled system which checks defined panel parameters on the four corners of a panel and related artwork for processing with a master pattern etched on a glass reference with a machine vision measuring system. The panel or artwork being checked is positioned by panel center registration means to align the center of the panel with the center of the master pattern. Displacement and rotational differences are entered under software control into a data base and analyzed by a stored program intelligent analyses system into a plurality of parameters based on a parameter model which permits an analysis of the cause of the misregistration.