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公开(公告)号：US20060043602A1
公开(公告)日：2006-03-02
申请号：US10932005
申请日：2004-09-02
Applicant: Kuo-Chin Chang , Simon Lu
Inventor： Kuo-Chin Chang , Simon Lu
IPC: H01L23/48
CPC classification number: H01L23/49838 , H01L23/49816 , H01L23/49833 , H01L23/562 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2224/0401
Abstract: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface of the substrate. A constraint member is secured to the lower surface of the substrate so that the constraint member has a degree of rigidity to reduce warpage due to thermal expansion mismatches between at least the microelectronic element and the substrate.
Abstract translation: 提供倒装芯片球栅阵列封装。 在一个实施例中，倒装芯片球栅阵列封装包括具有上表面和与上表面相对的下表面的衬底，以及包括一组焊球固定到衬底的上表面的微电子元件。 约束构件被固定到基板的下表面，使得约束构件具有刚度以减少由于至少微电子元件和基板之间的热膨胀错配引起的翘曲。
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公开(公告)号：US08492263B2
公开(公告)日：2013-07-23
申请号：US11941429
申请日：2007-11-16
Applicant: Chung Yu Wang , Chien-Hsiun Lee , Pei-Haw Tsao , Kuo-Chin Chang , Chung-Yi Lin , Bill Kiang
Inventor： Chung Yu Wang , Chien-Hsiun Lee , Pei-Haw Tsao , Kuo-Chin Chang , Chung-Yi Lin , Bill Kiang
IPC: H01L21/44
CPC classification number: H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05569 , H01L2224/05571 , H01L2224/056 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/11901 , H01L2224/13005 , H01L2224/13022 , H01L2224/13023 , H01L2224/13027 , H01L2224/131 , H01L2224/16 , H01L2224/45144 , H01L2224/48647 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/207 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
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公开(公告)号：US20120306067A1
公开(公告)日：2012-12-06
申请号：US13151720
申请日：2011-06-02
Applicant: Pei-Haw Tsao , Kuo-Chin Chang , Han-Ping Pu
Inventor： Pei-Haw Tsao , Kuo-Chin Chang , Han-Ping Pu
IPC: H01L23/488 , H01L23/36 , H01L21/50
CPC classification number: H01L21/568 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/92 , H01L2224/12105 , H01L2224/13022 , H01L2224/13111 , H01L2224/13147 , H01L2224/19 , H01L2224/215 , H01L2224/221 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/92244 , H01L2224/96 , H01L2924/01029 , H01L2924/10253 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2224/11 , H01L2924/00014 , H01L2924/01047 , H01L2924/0665 , H01L2924/00
Abstract: According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.
Abstract translation: 根据实施例，集成电路封装包括芯片，热部件和模制化合物。 芯片包括有源表面和与有源表面相对的背面。 热分量物理耦合到芯片的背面。 模塑料包封芯片，并且通过模塑料露出热组分的暴露表面。 另一实施例是形成集成电路封装的方法。
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公开(公告)号：US20120182694A1
公开(公告)日：2012-07-19
申请号：US13007249
申请日：2011-01-14
Applicant: Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
Inventor： Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
CPC classification number: H01L23/16 , H01L23/055 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.
Abstract translation: 在包装结构中，加强环在第一包装部件的顶表面上结合并结合。 第二包装部件在第一包装部件的顶部表面上结合并且被加强环环绕。 金属盖已经结合到加强环上。 金属盖具有通孔。
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公开(公告)号：US08174129B2
公开(公告)日：2012-05-08
申请号：US12853711
申请日：2010-08-10
Applicant: Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
Inventor： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
CPC classification number: H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。 半导体芯片可以安装在焊料凸块上。 硅基薄封装衬底可以用作半导体芯片的载体。
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Patent Agency Ranking
公开(公告)号：US07804177B2
公开(公告)日：2010-09-28
申请号：US11493375
申请日：2006-07-26
Applicant: Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
Inventor： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
CPC classification number: H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。 硅基薄封装衬底可以用作半导体芯片的载体。
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公开(公告)号：US20090130840A1
公开(公告)日：2009-05-21
申请号：US11941429
申请日：2007-11-16
Applicant: Chung Yu Wang , Chien-Hsiun Lee , Pei-Haw Tsao , Kuo-Chin Chang , Chung-Yi Lin , Bill Kiang
Inventor： Chung Yu Wang , Chien-Hsiun Lee , Pei-Haw Tsao , Kuo-Chin Chang , Chung-Yi Lin , Bill Kiang
IPC: H01L21/441
CPC classification number: H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05569 , H01L2224/05571 , H01L2224/056 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/11901 , H01L2224/13005 , H01L2224/13022 , H01L2224/13023 , H01L2224/13027 , H01L2224/131 , H01L2224/16 , H01L2224/45144 , H01L2224/48647 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/207 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
Abstract translation: 公开了焊球接头的保护，其中焊球接头位于封装缓冲层的表面水平以下。 蚀刻缓冲层以露出一个或多个电极柱，每个电极柱可以由单个柱或多个柱组成。 由顶部导电盖或电极柱周围的镀层产生的顶层也位于缓冲层的下方。 当焊球放置在柱上时，焊料/球窝接头被保护在缓冲层表面下方的位置，同时仍然保持各种焊球之间的电连接及其相关或封盖/电镀材料，电极柱 ，布线层和电路层。 因此，保护整个球窝接头免受直接的压力。
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公开(公告)号：US08519535B2
公开(公告)日：2013-08-27
申请号：US13105360
申请日：2011-05-11
Applicant: Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
Inventor： Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
CPC classification number: H01L23/562 , H01L23/3157 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15321 , H01L2924/3511 , H01L2924/00
Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.
Abstract translation: 一种方法包括确定集成电路（IC）封装设计的翘曲。 IC封装设计包括在第一主表面上具有顶部焊接掩模的基板和与第一主表面相对的第二主表面上的底部焊接掩模。 第一主表面上安装有IC芯片，顶部焊接掩模。 该设计被修改，包括修改由顶部焊接掩模和底部焊接掩模组成的组中的一个的平均厚度，以便减少翘曲。 根据改进的设计制造IC封装。
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公开(公告)号：US07932601B2
公开(公告)日：2011-04-26
申请号：US12899168
申请日：2010-10-06
Applicant: Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
Inventor： Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
CPC classification number: H01L24/11 , H01L24/81 , H01L2224/0231 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/1148 , H01L2224/116 , H01L2224/11902 , H01L2224/13019 , H01L2224/13076 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/81801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00
Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.
Abstract translation: 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。
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公开(公告)号：US20100301477A1
公开(公告)日：2010-12-02
申请号：US12853711
申请日：2010-08-10
Applicant: Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
Inventor： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC: H01L23/498 , H01L23/488
CPC classification number: H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。 半导体芯片可以安装在焊料凸块上。 硅基薄封装衬底可以用作半导体芯片的载体。
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