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    Semiconductor device less susceptible to viariation in threshold voltage
    11.
    发明申请
    Semiconductor device less susceptible to viariation in threshold voltage 失效
    半导体器件不太可能在阈值电压下发生变化

    公开(公告)号：US20040238875A1

    公开(公告)日：2004-12-02

    申请号：US10883807

    申请日：2004-07-06

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Hiroaki Nakai

    IPC: H01L029/76

    CPC classification number: G05F1/465 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.

    Abstract translation: 阈值补偿电路产生偏置电位VBIAS，即偏置给定值的MOS晶体管的阈值电压。 因此，对晶体管施加具有对阈值电压的变化的补偿的栅源电压。 通过使用具有该晶体管作为电流源的差分放大器，可以实现对由过程变化和温度引起的阈值电压变化较小的电压下变频器。

    Method of controlling communications
    12.
    发明申请
    Method of controlling communications 审中-公开
    控制通信的方法

    公开(公告)号：US20040233927A1

    公开(公告)日：2004-11-25

    申请号：US10679460

    申请日：2003-10-07

    Applicant: Renesas Technology Corp.

    Inventor： Takashi Hirosawa

    IPC: H04L012/413

    CPC classification number: H04L12/4015 ,  H04L12/413

    Abstract: In a network in which a plurality of terminals share one communication channel, signal collision is avoided and a predetermined signal is transmitted with a higher priority level. Priority levels are defined so that they are common to all the packets to be sent by nodes (including terminals and relating devices) on a network. Respective slots that regulate timing for sending out packets are assigned to the respective priority levels. Each slot is determined with reference to a time at which an ongoing packet transmission on the communication channel has finished. The priority levels are allocated in such a manner that packets having higher priority levels (packets to be sent out with higher priority) are allocated to slots having earlier timing.

    Abstract translation: 在多个终端共享一个通信信道的网络中，避免信号冲突，并以更高的优先级发送预定的信号。 定义优先级，使得它们对于由网络上的节点（包括终端和相关设备）发送的所有分组是共同的。 调整发送数据包的定时的各个时隙被分配给相应的优先级。 参考通信信道上正在进行的分组传输已经完成的时间来确定每个时隙。 分配优先级，使得具有较高优先级的分组（具有较高优先级的要发送的分组）被分配给具有较早定时的时隙。

    Thin film magnetic memory device for selectively supplying a desired data write current to a plurality of memory blocks
    13.
    发明申请
    Thin film magnetic memory device for selectively supplying a desired data write current to a plurality of memory blocks 有权
    薄膜磁存储器件，用于向多个存储块选择性地提供期望的数据写入电流

    公开(公告)号：US20040218452A1

    公开(公告)日：2004-11-04

    申请号：US10851159

    申请日：2004-05-24

    Applicant: RENESAS TECHNOLOGY CORP

    Inventor： Takaharu Tsuji

    IPC: G11C007/00

    CPC classification number: G11C11/15

    Abstract: Each of N memory blocks of first to Nth stages includes a plurality of first and second driver units. The plurality of first and second driver units are respectively provided corresponding to one end and another end of a plurality of digit lines included in each memory block. Each of the first driver units in memory blocks before a selected memory block connects a corresponding digit line to a first voltage according to a voltage level on a digit line of the same row in a memory block of a previous stage. A second driver unit in the selected memory block connects a corresponding digit line to a second voltage in order to supply a data write current. In other words, digit lines in the memory blocks before the selected memory block are not used as current lines but as signal lines.

    Processing method of semiconductor substrate
    14.
    发明申请
    Processing method of semiconductor substrate 审中-公开
    半导体衬底的加工方法

    公开(公告)号：US20040203257A1

    公开(公告)日：2004-10-14

    申请号：US10697277

    申请日：2003-10-31

    Applicant: Renesas Technology Corp.

    Inventor： Takeshi Yoshida ,  Tohru Koyama ,  Yoji Mashiko

    IPC: H01L021/26 ,  H01L021/00 ,  G02B003/00 ,  H01L031/0232 ,  C03C015/00

    CPC classification number: H01L21/268 ,  G02B3/00

    Abstract: A processing technique of a semiconductor substrate which can improve a capability of a solid immersion lens in case of processing the semiconductor substrate and forming the solid immersion lens on its surface is provided. A focused ion beam (5) is irradiated on a semiconductor substrate (1), and a salient part (2) acting as a solid immersion lens is formed on its main surface (3a). At this time, a cutting amount of the semiconductor substrate (1) by the focused ion beam (5) is adjusted by making the irradiation time of the focused ion beam (5) to the semiconductor substrate (1) change. According to this, a surface of the salient part (2) has a curved surface of high precision, and a capability of the salient part (2) as the solid immersion lens is improved.

    Abstract translation: 提供了半导体衬底的处理技术，其可以在处理半导体衬底并在其表面上形成固体浸没透镜的情况下提高固体浸没透镜的能力。 聚焦离子束（5）照射在半导体衬底（1）上，并且在其主表面（3a）上形成用作固体浸没透镜的突出部分（2）。 此时，通过使聚焦离子束（5）对半导体基板（1）的照射时间发生变化来调整通过聚焦离子束（5）的切割量的半导体基板（1）。 据此，突出部（2）的表面具有高精度的曲面，提高了作为固体浸没透镜的突出部（2）的能力。

    Asynchronous data transmitting apparatus
    15.
    发明申请
    Asynchronous data transmitting apparatus 有权
    异步数据发送装置

    公开(公告)号：US20040202253A1

    公开(公告)日：2004-10-14

    申请号：US10731026

    申请日：2003-12-10

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Toshiaki Hanibuchi

    IPC: H04B003/00

    CPC classification number: H04L25/14 ,  H04L7/0008

    Abstract: An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal through the data signal transmission lines, depending on a transmit clock; and control transmitting units that transmit control signals through the control transmission lines, depending on the transmit clock. The receiver includes a receive clock generator that generates a read clock from the control signals; and a data receiving unit that receives the data signal through the data signal transmission line, depending on the read clock.

    Abstract translation: 异步数据发送装置包括数据信号传输线; 分别具有最小延迟和最大延迟的两个控制传输线; 发射机 和接收器。 发射机包括数据发送单元，其根据发送时钟通过数据信号传输线路发送数据信号; 以及根据发送时钟通过控制传输线路发送控制信号的控制发送单元。 接收机包括从控制信号产生读时钟的接收时钟发生器; 以及数据接收单元，其根据读取的时钟通过数据信号传输线接收数据信号。

    Semiconductor device
    16.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20040201062A1

    公开(公告)日：2004-10-14

    申请号：US10653198

    申请日：2003-09-03

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Masakazu Hirose ,  Fukashi Morishita

    IPC: H01L027/01

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.

    Abstract translation: 在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。 提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。 类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。 通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。

    Non-volatile semiconductor memory device attaining high data transfer rate
    18.
    发明申请
    Non-volatile semiconductor memory device attaining high data transfer rate 有权
    非易失性半导体存储器件达到高数据传输速率

    公开(公告)号：US20040196696A1

    公开(公告)日：2004-10-07

    申请号：US10665010

    申请日：2003-09-22

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Tadaaki Yamauchi

    IPC: G11C011/34

    CPC classification number: G11C16/28

    Abstract: A reference cell is connected to two reference bit lines. In data access, when one reference bit line is driven to a selected state in response to a reference column select signal which is a decode result of a column address, a potential of a selected reference bit line is transmitted to a reference data bus line. A potential difference between the reference data bus line and a data bus line is amplified by a sense amplifier, and read data is output from an external terminal. During the access period, a reference bit line in a non-selected state is precharged to a ground potential in response to a reset signal at H level. In the next data access, when the non-selected reference bit line is selected, successive data reading is attained without waiting for a time period for precharging a bit line.

    Abstract translation: 参考单元连接到两个参考位线。 在数据访问中，当响应于作为列地址的解码结果的参考列选择信号将一个参考位线驱动到选择状态时，所选择的参考位线的电位被发送到参考数据总线。 参考数据总线与数据总线之间的电位差由读出放大器放大，从外部端子输出读取数据。 在访问期间，响应于H电平的复位信号，未选择状态的参考位线被预充电到地电位。 在接下来的数据访问中，当选择未选择的参考位线时，连续读取数据，而不用等待预定位线的时间段。

    Nonvolatile memory device and semiconductor device
    19.
    发明申请
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US20040196695A1

    公开(公告)日：2004-10-07

    申请号：US10805365

    申请日：2004-03-22

    Applicant: Renesas Technology Corp.

    Inventor： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC: G11C011/34

    CPC classification number: G11C16/10 ,  G11C16/0433

    Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

    Abstract translation: 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

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