公开(公告)号：US08969969B2

公开(公告)日：2015-03-03

申请号：US12727312

申请日：2010-03-19

Applicant: Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, Jr.

Inventor： Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, Jr.

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823412

Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

公开(公告)号：US20100207246A1

公开(公告)日：2010-08-19

申请号：US12699601

申请日：2010-02-03

Applicant: Roger Allen Booth, JR. ,  Kangguo Cheng

Inventor： Roger Allen Booth, JR. ,  Kangguo Cheng

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/87

Abstract: A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

Abstract translation: 一种形成具有交错电容器板的MIM电容器的方法。 金属和电介质层交替沉积在绝缘体材料层的开口中。 在每次沉积金属层之后，从侧面以一角度去除金属层以形成电容器板。 去除金属层的一侧与沉积的每个金属层交替。 当所有电容器板已经形成时，绝缘体材料层中剩余的开口被电介质材料填充，然后平坦化，随后与电容器板形成接触。 还有一种具有交错电容器板的MIM电容器结构。

公开(公告)号：US08409989B2

公开(公告)日：2013-04-02

申请号：US12944174

申请日：2010-11-11

Applicant: Chengwen Pei ,  Roger Allen Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

Inventor： Chengwen Pei ,  Roger Allen Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/72

CPC classification number: H01L29/49 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Abstract translation: 公开了一种在晶体管上制造体接触的结构和方法。 该方法包括在处理晶片上形成具有晶体管的半导体结构。 然后将结构反转，并移除手柄晶片。 然后在倒置位置的晶体管上形成硅化物体接触。 身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

公开(公告)号：US08288240B2

公开(公告)日：2012-10-16

申请号：US12699601

申请日：2010-02-03

Applicant: Roger Allen Booth, Jr. ,  Kangguo Cheng

Inventor： Roger Allen Booth, Jr. ,  Kangguo Cheng

IPC: H01L21/02

CPC classification number: H01L28/87

Abstract: A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

Abstract translation: 一种形成具有交错电容器板的MIM电容器的方法。 金属和电介质层交替沉积在绝缘体材料层的开口中。 在每次沉积金属层之后，从侧面以一角度去除金属层以形成电容器板。 去除金属层的一侧与沉积的每个金属层交替。 当所有电容器板已经形成时，绝缘体材料层中剩余的开口被电介质材料填充，然后被平坦化，随后与电容器板形成接触。 还有一种具有交错电容器板的MIM电容器结构。

公开(公告)号：US07863122B2

公开(公告)日：2011-01-04

申请号：US12133440

申请日：2008-06-05

Applicant: Roger Allen Booth, Jr. ,  William Paul Hovis ,  Jack Allan Mandelman

Inventor： Roger Allen Booth, Jr. ,  William Paul Hovis ,  Jack Allan Mandelman

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.

Abstract translation: finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。

公开(公告)号：US20100237425A1

公开(公告)日：2010-09-23

申请号：US12727312

申请日：2010-03-19

Applicant: Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

Inventor： Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823412

Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Abstract translation: 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

公开(公告)号：US20100193854A1

公开(公告)日：2010-08-05

申请号：US12692923

申请日：2010-01-25

Applicant: Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

Inventor： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC: H01L29/76 ,  H01L21/335

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).

Abstract translation: 热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。 半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。

公开(公告)号：US07692250B2

公开(公告)日：2010-04-06

申请号：US11927110

申请日：2007-10-29

Applicant: Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

Inventor： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

IPC: H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract translation: 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

公开(公告)号：US07667248B2

公开(公告)日：2010-02-23

申请号：US12028916

申请日：2008-02-11

Applicant: Roger Allen Booth, Jr. ,  William Paul Hovis ,  Jack Allan Mandelman

Inventor： Roger Allen Booth, Jr. ,  William Paul Hovis ,  Jack Allan Mandelman

IPC: H01L29/00

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.

Abstract translation: finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。

公开(公告)号：US07352034B2

公开(公告)日：2008-04-01

申请号：US11211956

申请日：2005-08-25

Applicant: Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

Inventor： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

IPC: H01L29/94

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract translation: 通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。