公开(公告)号：US20250149394A1

公开(公告)日：2025-05-08

申请号：US19018792

申请日：2025-01-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Kalyani KODURI ,  Leslie Edward STARK

IPC: H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

公开(公告)号：US12294985B2

公开(公告)日：2025-05-06

申请号：US17387692

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yaron Alpert ,  Maxim Altshul ,  Maital Hahn ,  Chia-Jung Lee

IPC: H04W72/12 ,  H04W4/80 ,  H04W72/1263

Abstract: A device (e.g., a BLUETOOTH device) includes memory and one or more processors coupled to the memory. The one or more processors are configured to implement a BLUETOOTH host, a BLUETOOTH host-controller interface, and a BLUETOOTH controller. The one or more processors are further configured to cause the BLUETOOTH controller to receive, from the BLUETOOTH host via the BLUETOOTH host-controller interface, a message indicating first channel and timing information for sending data corresponding to a BLUETOOTH application. The one or more processors are further configured to cause the BLUETOOTH controller to initiate sending the data based on the first channel and timing information.

公开(公告)号：US12294384B2

公开(公告)日：2025-05-06

申请号：US18086204

申请日：2022-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishal Shaw ,  Preetam Charan Anand Tadeparthy ,  Mayank Jain

IPC: H03M1/82 ,  G06F1/26 ,  H03K5/156 ,  H03K7/08 ,  H03M1/06 ,  H03M1/12

Abstract: In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

公开(公告)号：US20250140708A1

公开(公告)日：2025-05-01

申请号：US18987433

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US20250140626A1

公开(公告)日：2025-05-01

申请号：US18495837

申请日：2023-10-27

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.

公开(公告)号：US20250139035A1

公开(公告)日：2025-05-01

申请号：US19010323

申请日：2025-01-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Sanand PRASAD

IPC: G06F13/28 ,  G06F13/42

Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

公开(公告)号：US20250139019A1

公开(公告)日：2025-05-01

申请号：US19004607

申请日：2024-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

公开(公告)号：US20250138148A1

公开(公告)日：2025-05-01

申请号：US18499181

申请日：2023-10-31

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Piyush Soni ,  Vashishth Dudhia ,  Ryan Smith ,  Kavithaa Rajagopalan ,  Karthik Ramasubramanian ,  Shankar Ram Narayana Moorthy ,  Indu Prathapan ,  Samala Sreekiran

IPC: G01S7/40 ,  G01S13/32

Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar includes a reference clock, a phase locked loop (PLL), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. The reference clock generates a reference clock signal. The PLL generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. The pulse generator outputs a chirp start pulse in response to the reference clock signal. The counter increments a count in response to the feedback clock signal. The synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. The chirp ramp control circuit causes the PLL to ramp a frequency of the output signal in response to the chirp ramp signal.

公开(公告)号：US20250138054A1

公开(公告)日：2025-05-01

申请号：US18499086

申请日：2023-10-31

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Dok Won Lee ,  Hank Ming Sung ,  Kenji Otake

IPC: G01R15/20 ,  G01R19/00 ,  H10N52/01 ,  H10N52/80

Abstract: A described example includes: a heat slug coupled to a package substrate, the heat slug configured to conduct a current between terminals of the package substrate; a first magnetic shield mounted to a top surface of the package substrate, the first magnetic shield including a die mount area; a semiconductor die flip chip mounted to the die mount area; a second magnetic shield mounted to the package substrate, the second magnetic shield having a cantilever portion extending over a portion of the semiconductor die including a Hall element; electrical connections of wire bonds or ribbon bonds between bond pads of the semiconductor die and leads on the package substrate; and mold compound covering the electrical connections, the semiconductor die, the first magnetic shield, and the second magnetic shield, while a portion of the heat slug is exposed forming a thermal pad for a semiconductor device package.

公开(公告)号：US12289638B2

公开(公告)日：2025-04-29

申请号：US18327338

申请日：2023-06-01

Applicant: Texas Instruments Incorporated

Inventor： Oren Aharon Shani ,  Shai Erez ,  Matan Ben-Shachar

IPC: H04W84/12 ,  H04L1/1607 ,  H04W28/06 ,  H04W52/02 ,  H04W80/02

Abstract: A wireless station (STA) in a wireless local area network (WLAN) performs a method to avoid media access control (MAC) padding of a physical layer convergence protocol data unit (PPDU) (e.g., a trigger-based (TB) PPDU, etc.). The method can reduce current or power consumption by the STA, which can in turn optimize the STA and, in certain instances, the WLAN as whole. In one example, the method includes the STA receiving a trigger frame from an access point (AP). The trigger frame specifies a length of a PPDU. The method further includes the STA generating a TB PPDU based on the specifications in the trigger frame. In particular, the STA generates a PPDU that has a length that is less than the length specified by the trigger frame. The method also includes the STA transmitting the generated PPDU to the AP.