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公开(公告)号：US3445168A
公开(公告)日：1969-05-20
申请号：US3445168D
申请日：1965-10-28
Applicant: VISHAY INTERTECHNOLOGY INC
Inventor： ZANDMAN FELIX , POST DANIEL
IPC: G01B11/16
CPC classification number: G01B11/165
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公开(公告)号：US10770489B2
公开(公告)日：2020-09-08
申请号：US15941855
申请日：2018-03-30
Applicant: VISHAY INTERTECHNOLOGY, INC.
Inventor： Koon-Wing Tsang , Yuh-Min Lin
IPC: H01L27/144 , H01L31/0216 , G01J3/02 , G01J3/28
Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.
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公开(公告)号：US20040041278A1
公开(公告)日：2004-03-04
申请号：US10440941
申请日：2003-05-19
Applicant: Vishay Intertechnology, Inc.
Inventor： Leonid Akhtman , Sakaev Matvey
IPC: H05K001/03 , H05K001/16
CPC classification number: H01C7/003 , H01C1/142 , H01C17/006 , H01C17/281 , Y10T29/49082 , Y10T29/49098 , Y10T29/49099
Abstract: The present invention provides for a flip chip resistor having a substrate having opposite ends, a pair of electrodes formed from a first electrode layer disposed on the opposite ends of the substrate, a resistance layer electrically connecting the pair of electrodes, a protective layer overlaying the resistance layer, and a second electrode layer overlaying the first electrode layer and at least a portion of the protective layer. The present invention provides for higher reliability performance and enlarging the potential soldering area despite small chip size. A method of the present invention provides for manufacturing flip chip resistors by applying a first electrode layer to a substrate to create at least one pair of opposite electrodes, applying a resistance layer between each pair of opposite electrodes; applying a first protective layer at least partially overlaying the resistance layer, applying a second protective layer at least partially overlaying at least a portion of the resistance layer, and applying a second electrode layer overlaying the first electrode layer and at least a portion of the second protective layer.
Abstract translation: 本发明提供一种具有相对端的衬底的倒装芯片电阻器，由设置在衬底的相对端上的第一电极层形成的一对电极，电连接该对电极的电阻层，覆盖 电阻层和覆盖第一电极层和保护层的至少一部分的第二电极层。 尽管芯片尺寸小，本发明提供了更高的可靠性性能和扩大了潜在的焊接区域。 本发明的方法提供了制造倒装芯片电阻器，通过向基片施加第一电极层以产生至少一对相对电极，在每对相对电极之间施加电阻层; 施加至少部分地覆盖所述电阻层的第一保护层，施加至少部分覆盖所述电阻层的至少一部分的第二保护层，以及施加覆盖所述第一电极层的第二电极层和所述第二电极层的至少一部分 保护层。
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14.发明申请Chip scale surface mount package for semiconductor device and process of fabricating the same 有权用于半导体器件的芯片级表面贴装封装及其制造方法公开(公告)号：US20020185710A1
公开(公告)日：2002-12-12
申请号：US10157584
申请日：2002-05-28
Applicant: Vishay Intertechnology, Inc.
Inventor： Felix Zandman , Y. Mohammed Kasem , Yueh-Se Ho
IPC: H01L021/44 , H01L023/544 , H01L029/06
CPC classification number: H01L21/76898 , H01L23/3107 , H01L23/3114 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01079 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
Abstract translation: 在晶片尺寸上制造在骰子的两侧形成触点的半导体封装。 晶片的背面附着在金属板上。 分割骰子的划痕线被锯切以暴露金属板，但切口不延伸通过金属板。 可以包括多个子层的金属层形成在骰子的前侧，金属覆盖金属板的暴露部分并延伸骰子的侧边缘。 金属层的分开的部分也可以覆盖骰子正面上的连接垫。 使用与用于制造第一组锯切的刀片相比较窄的第二组锯切与第一组锯切重合。 结果，金属层保留在连接骰子（通过金属板）的前侧和前侧的骰子的侧边缘上。 由于不需要引线键合，所以产生的封装是坚固的，并且在芯片的背面和前面之间提供低电阻电连接。
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公开(公告)号：US3782182A
公开(公告)日：1974-01-01
申请号：US3782182D
申请日：1971-04-29
Applicant: VISHAY INTERTECHNOLOGY INC
Inventor： STARR J
CPC classification number: G01B7/18 , G01L1/2206
Abstract: A strain multiplier is provided which is designed to be firmly attached to both a structural surface and a sensing gage at all points of contact between the multiplier and the structural surface and the multiplier and the sensing gage while preventing direct contact between the sensing gage and the structural surface.
Abstract translation: 提供了一种应变倍增器，其被设计成在乘法器和结构表面以及乘法器和感测量规之间的所有接触点牢固地附接到结构表面和感测量规，同时防止感测量规和 结构面。
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Patent Agency Ranking
公开(公告)号：US3517436A
公开(公告)日：1970-06-30
申请号：US70179467
申请日：1967-11-01
Applicant: VISHAY INTERTECHNOLOGY INC
Inventor： ZANDMAN FELIX , BOYD BRANIN A
IPC: H01C1/024 , H01C7/06 , H01C17/232 , H01C17/24 , H01C17/245 , H01C1/02 , H01C17/00
CPC classification number: H01C1/024 , H01C7/06 , H01C17/232 , H01C17/2416 , H01C17/245 , Y10T29/49087 , Y10T29/49099
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公开(公告)号：US08957756B2
公开(公告)日：2015-02-17
申请号：US13970011
申请日：2013-08-19
Applicant: Vishay Intertechnology, Inc.
Inventor： Michael Belman , Leonid Akhtman
CPC classification number: H01C1/034 , H01C17/288
Abstract: A chip resistor includes an insulating substrate, top terminal electrodes formed on top surface of the substrate using silver-based cermet, bottom electrodes, resistive element that is situated between the top terminal electrodes and overlaps them partially, an optional internal protective coating that covers resistive element completely or partially, an external protective coating that covers completely the internal protection coating and partially covers top terminal electrodes, a plated layer of nickel that covers face sides of the substrate, top and bottom electrodes, and overlaps partially external protective coating, finishing plated layer that covers nickel layer. The overlap of nickel layer and external protective layer possesses a sealing property because of metallization of the edges of external protective layer prior to the nickel plating process.
Abstract translation: 片状电阻器包括绝缘基板，使用银基金属陶瓷在基板的顶表面上形成的顶端电极，底电极，位于顶端电极之间并与其部分重叠的电阻元件，可选的内部保护涂层，其覆盖电阻 元件完全或部分，外部保护涂层完全覆盖内部保护涂层，并部分覆盖顶端电极，覆盖基板正面的镍镀层，顶部和底部电极，并重叠部分外部保护涂层，镀层 覆盖镍层的层。 镍镀层和外部保护层的重叠由于在镀镍工艺之前的外部保护层的边缘的金属化而具有密封性。
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公开(公告)号：US20130335191A1
公开(公告)日：2013-12-19
申请号：US13970011
申请日：2013-08-19
Applicant: Vishay Intertechnology, Inc.
Inventor： Michael Belman , Leonid Akhtman
IPC: H01C1/034
CPC classification number: H01C1/034 , H01C17/288
Abstract: A chip resistor includes an insulating substrate, top terminal electrodes formed on top surface of the substrate using silver-based cermet, bottom electrodes, resistive element that is situated between the top terminal electrodes and overlaps them partially, an optional internal protective coating that covers resistive element completely or partially, an external protective coating that covers completely the internal protection coating and partially covers top terminal electrodes, a plated layer of nickel that covers face sides of the substrate, top and bottom electrodes, and overlaps partially external protective coating, finishing plated layer that covers nickel layer. The overlap of nickel layer and external protective layer possesses a sealing property because of metallization of the edges of external protective layer prior to the nickel plating process.
Abstract translation: 片状电阻器包括绝缘基板，使用银基金属陶瓷在基板的顶表面上形成的顶端电极，底电极，位于顶端电极之间并与其部分重叠的电阻元件，可选的内部保护涂层，其覆盖电阻 元件完全或部分，外部保护涂层完全覆盖内部保护涂层，并部分覆盖顶端电极，覆盖基板正面的镍镀层，顶部和底部电极，并重叠部分外部保护涂层，镀层 覆盖镍层的层。 镍镀层和外部保护层的重叠由于在镀镍工艺之前的外部保护层的边缘的金属化而具有密封性。
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19.发明授权
公开(公告)号：US3601744A
公开(公告)日：1971-08-24
申请号：US3601744D
申请日：1969-07-14
Applicant: VISHAY INTERTECHNOLOGY INC
Inventor： ZANDMAN FELIX
CPC classification number: H01C10/308 , H01C10/06 , H01C10/40
Abstract: An adjustable resistor wherein a predetermined pattern of thin metallic film is deposited upon a substrate, a thin isolating layer being interposed between the substrate and film, and a movable contact system with suitable linear or rotary mechanical drive means is arranged for movability parallel to the substrate surface on which are fixed the isolating layer and metallic film, the contact system providing connection to the metallic film at a distance from one end thereof dependent on the position of the drive means. The pattern in the metallic film compels the electric current to flow through a path of limited width and of effective length much greater than the straightline length along the midline of the pattern.
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