公开(公告)号：US10649944B2

公开(公告)日：2020-05-12

申请号：US15633431

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Gopi Krishnamurthy

IPC: G06F13/40 ,  G06F13/42

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

公开(公告)号：US09438272B1

公开(公告)日：2016-09-06

申请号：US14331933

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Chong H. Lee

IPC: H04L7/00 ,  H03M9/00

CPC classification number: H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract translation: 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

公开(公告)号：US20150019777A1

公开(公告)日：2015-01-15

申请号：US13942532

申请日：2013-07-15

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Gopi Krishnamurthy

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  G06F13/4282

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract translation: 使用高速串行链路配置可配置的从设备的机制和技术，其中使用不同数量的高速串行链路的通道来在从设备和主设备之间发送数据，这取决于从设备是否在配置中 模式或正常操作模式。

公开(公告)号：US08804890B2

公开(公告)日：2014-08-12

申请号：US13907158

申请日：2013-05-31

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Chong H. Lee

IPC: H04L7/00

CPC classification number: H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract translation: 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

公开(公告)号：US20170357606A1

公开(公告)日：2017-12-14

申请号：US15633431

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Gopi Krishnamurthy

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4282

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

公开(公告)号：US09660630B1

公开(公告)日：2017-05-23

申请号：US15295918

申请日：2016-10-17

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Dana How ,  Christopher Lane

IPC: H03H11/26 ,  H03K5/159 ,  H03L7/08 ,  H03K5/00

CPC classification number: H03L7/0807 ,  G06F1/10 ,  H03K3/01 ,  H03K5/159 ,  H03K19/1774 ,  H03K2005/00019 ,  H03L7/0812

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

公开(公告)号：US09077341B1

公开(公告)日：2015-07-07

申请号：US13802752

申请日：2013-03-14

Applicant: Altera Corporation

Inventor： Catherine Chingi Chang ,  Henry Y. Liu ,  Ramanand Venkata

IPC: H03K19/177

CPC classification number: H03K19/17748

Abstract: In an embodiment of the present invention, a programmable matrix is provided for flexibly allocating communication resources among functional circuit blocks. For example, in an embodiment of the present invention, a programmable matrix is provided that allocations communications channels such as transceiver channels among various PCIe hard IP blocks that may be contained within a programmable logic device (PLD).

Abstract translation: 在本发明的实施例中，提供了一种用于在功能电路块之间灵活分配通信资源的可编程矩阵。 例如，在本发明的一个实施例中，提供了一种可编程矩阵，其可以将可能包含在可编程逻辑器件（PLD）内的各种PCIe硬IP块中的诸如收发器通道的通信信道分配。

公开(公告)号：US08692595B1

公开(公告)日：2014-04-08

申请号：US13829995

申请日：2013-03-14

Applicant: Altera Corporation

Inventor： David W. Mendel ,  Sergey Shumarayev ,  Ramanand Venkata

IPC: H03L7/18 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03L7/183

Abstract: An integrated circuit with at least two LC-based phase-locked loop circuits and a high-speed serial interface circuit having multiple channels is provided. Each phase-locked loop circuit may include an oscillator having a varactor and multiple inductors. The oscillator may be configured to generate signals at different frequency ranges as determined by the inductors and the varactor. The LC-based phase-locked loop circuits may be produced such that all frequency ranges together provide the continuous coverage of an octave, thereby enabling the phase-locked loop circuits to generate a clock signal with high quality factors and desirable phase noise and jitter performance at an arbitrary frequency. Since the channels of the high-speed serial interface circuit may receive a clock signal having an arbitrary frequency, the high-speed serial interface circuit may be configured to support any communications protocol.

Abstract translation: 提供具有至少两个基于LC的锁相环电路的集成电路和具有多个通道的高速串行接口电路。 每个锁相环电路可以包括具有变容二极管和多个电感器的振荡器。 振荡器可以被配置为产生由电感器和变容二极管确定的不同频率范围的信号。 可以产生基于LC的锁相环电路，使得所有频率范围一起提供八度音程的连续覆盖，从而使得锁相环电路能够产生具有高质量因素的时钟信号和期望的相位噪声和抖动性能 以任意频率。 由于高速串行接口电路的信道可以接收具有任意频率的时钟信号，所以高速串行接口电路可以被配置为支持任何通信协议。