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公开(公告)号：US20180074824A1
公开(公告)日：2018-03-15
申请号：US15264002
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Ali Sazegari , Eric Bainville , Jeffry E. Gonion , Gerard R. Williams, III , Andrew J. Beaumont-Smith
CPC classification number: G06F9/30101 , G06F9/3001 , G06F9/30036 , G06F9/30043 , G06F9/3802 , G06F9/3867 , G06F9/3877 , G06F9/3893
Abstract: In an embodiment, an outer product engine is configured to perform outer product operations. The outer product engine may perform numerous multiplication operations in parallel on input vectors, in an embodiment, generating a resulting outer product matrix. In an embodiment, the outer product engine may be configured to accumulate results in a result matrix, performing fused multiply add (FMA) operations to produce the outer product elements (multiply) and to accumulate the outer product elements with previous elements from the result matrix memory (add). A processor may fetch outer product instructions, and may transmit the instructions to the outer product engine when the instructions become non-speculative in an embodiment. The processor may be configured to retire the outer product instructions responsive to transmitting them to the outer product engine.
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公开(公告)号：US20180054630A1
公开(公告)日：2018-02-22
申请号：US15242276
申请日：2016-08-19
Applicant: Apple Inc.
Inventor： Paul Chang , Ali Sazegari , Eric Bainville
CPC classification number: H04N19/91 , G06T9/005 , H04N19/12 , H04N19/136 , H04N19/17 , H04N19/186 , H04N19/21 , H04N19/27 , H04N19/85
Abstract: A hybrid compression method for compressing images is provided. The method identifies a first set of image components to be compressed by a lossy compression format and a second set of image components to be compressed by a lossless compression format. The method then encodes the first set of image components according to the lossy compression format and encodes the second set of image components according to the lossless compression format. The method then generates a compressed structure that includes the lossy-compressed first set of image components and the lossless-compressed second set of image components.
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公开(公告)号：US12184309B2
公开(公告)日：2024-12-31
申请号：US18077196
申请日：2022-12-07
Applicant: Apple Inc.
Inventor： Christian T. Martelock , Ali Sazegari , Eric Bainville
IPC: H03M7/30 , G06F40/211 , H03M7/42
Abstract: A method for encoding text includes grouping text as a sequence of bytes, the text comprising a string of characters, each byte corresponding to a character in the text. For each byte of the sequence of bytes: (a) each bit is processed from most significant bit to least significant bit to generate a context; and (b) a subsequent bit is predicted, using a prediction model, based on the context generated based on previously processed bits, prediction of the prediction model being a combination of predictions of a plurality of sub-models. An encoded bitstream is output based on the predicted bits. The encoded bitstream includes encoded data corresponding to the text.
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公开(公告)号：US12118332B2
公开(公告)日：2024-10-15
申请号：US18045577
申请日：2022-10-11
Applicant: Apple Inc.
Inventor： Ali Sazegari , Segev Elmalem , O-Cheng Chang , Jingwei Zhang , Ido Soffair , Aaftab A. Munshi
IPC: G06F7/552
CPC classification number: G06F7/552
Abstract: Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y log2x. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques.
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公开(公告)号：US20230393830A1
公开(公告)日：2023-12-07
申请号：US17898013
申请日：2022-08-29
Applicant: Apple Inc.
Inventor： Christian T. Martelock , Ali Sazegari , Eric Bainville
CPC classification number: G06F8/63 , G06F8/658 , G06F9/44505
Abstract: Aspects and features include using a virtual disk image to improve computational performance when applying a software patch. Compressed extents within a stored disk image are detected. The compressed extents are virtually reordered to form compressed forks within a virtual disk image and the compressed forks are selected for decompression based on code to be patched. A decompressed fork with the patch is virtually written to the same or another virtual disk image as an updated fork, and the virtual disk image is used to write to storage, either to overwrite the same stored disk image or to produce an updated, compressed disk image. In some examples, the virtual disk image is validated prior to writing to the compressed image by comparing an output hash from the compressed disk image with a known hash to validate the virtual disk image.
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Patent Agency Ranking
公开(公告)号：US20210342154A1
公开(公告)日：2021-11-04
申请号：US17373144
申请日：2021-07-12
Applicant: Apple Inc.
Inventor： Eric Bainville , Ali Sazegari
Abstract: In an embodiment, a processor supports one or more compression assist instructions which may be employed in compression software to improve the performance of the processor when performing compression/decompression. That is, the compression/decompression task may be performed more rapidly and consume less power when the compression assist instructions are employed then when they are not. In some cases, the cost of a more effective, more complex compression algorithm may be reduced to the cost of a less effective, less complex compression algorithm.
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公开(公告)号：US10853446B2
公开(公告)日：2020-12-01
申请号：US16144318
申请日：2018-09-27
Applicant: Apple Inc.
Inventor： Chris C. Lee , Ali Sazegari
Abstract: In one embodiment, a computer-implemented method of discrete Fourier transform (DPT), FFT, or DCT computations on a system comprising a processor is described herein. In one example, the method includes receiving, with the processor, input complex samples from memory of the system, determining input vectors based on the received input complex samples, determining a DFT radix p of p macro blocks based on the input vectors, determining p independent DFT-L vectors based on the p macro blocks with L being based on p, and generating p DFT-N output vectors without reordering or shuffling output data based on the p independent DFT-L vectors.
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公开(公告)号：US20200272464A1
公开(公告)日：2020-08-27
申请号：US16818200
申请日：2020-03-13
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Erik Norden , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.
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公开(公告)号：US10754649B2
公开(公告)日：2020-08-25
申请号：US16043772
申请日：2018-07-24
Applicant: Apple Inc.
Inventor： Eric Bainville , Jeffry E. Gonion , Ali Sazegari , Gerard R. Williams, III
Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.
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公开(公告)号：US10599427B2
公开(公告)日：2020-03-24
申请号：US15955417
申请日：2018-04-17
Applicant: Apple Inc.
Inventor： Eric Bainville , Ali Sazegari
Abstract: A novel software updating method is provided. A target file is divided into segments, where some segments are updated by patching, while other segments are updated by archiving. The segmentation of the update allows very large files such as DYLD shared caches to be patched in-place, i.e., by using free space available within the file to perform patching rather than requiring enough free space on disk to store both the new version and the old version of the file. The segmentation of the update also allows each segment to be updated individually by the most optimal update method (copy, patch, or archive) so that the size of the update file can be minimized.
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