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    FENCE MANAGEMENT OVER MULTIPLE BUSSES
    11.
    发明申请
    FENCE MANAGEMENT OVER MULTIPLE BUSSES 有权
    多个总线的财务管理

    公开(公告)号：US20150149673A1

    公开(公告)日：2015-05-28

    申请号：US14089237

    申请日：2013-11-25

    Applicant: Apple Inc.

    Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

    IPC: G06F13/40 ,  G06F13/362

    CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

    Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

    Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。

    System Control Using Sparse Data
    12.
    发明申请
    System Control Using Sparse Data 有权

    公开(公告)号：US20250013576A1

    公开(公告)日：2025-01-09

    申请号：US18777905

    申请日：2024-07-19

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

    IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

    Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

    System control using sparse data
    14.
    发明授权
    System control using sparse data 有权

    公开(公告)号：US11327896B2

    公开(公告)日：2022-05-10

    申请号：US16908182

    申请日：2020-06-22

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

    IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

    Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

    System Control Using Sparse Data
    15.
    发明申请
    System Control Using Sparse Data 审中-公开

    公开(公告)号：US20200320013A1

    公开(公告)日：2020-10-08

    申请号：US16908182

    申请日：2020-06-22

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

    IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

    Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

    Hardware state data logger for silicon debug
    17.
    发明授权
    Hardware state data logger for silicon debug 有权
    用于硅调试的硬件状态数据记录器

    公开(公告)号：US09448872B2

    公开(公告)日：2016-09-20

    申请号：US14179191

    申请日：2014-02-12

    Applicant: Apple Inc.

    Inventor： Ben D. Jarrett ,  Fritz A. Boehm

    IPC: G06F17/50 ,  G06F11/07 ,  G01R31/317 ,  G06F11/22

    CPC classification number: G06F11/0778 ,  G01R31/31705 ,  G06F11/22 ,  G06F11/3476 ,  G06F17/40

    Abstract: Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.

    Abstract translation: 利用硬件状态数据记录器在硅中进行调试的系统和方法。 将一个或多个硬件状态数据记录器结合到电路设计中并与电路的功能单元一起制造成制造的芯片。 当在制造的芯片的测试期间遇到问题时，硬件状态数据记录器能够捕获并存储导致错误的最终事件序列。 然后从制造的芯片中提取存储的数据，并用于确定故障的根本原因。

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